01-04-2010 02:38 AM
The chip being used is Vertix5 LX155T.
I use MGT122 for SRIO, the input and output pins of tile1 are conected directly for self loopback test, and those of tile0 are conected with DSP's SRIO.
I use the example programmes, when the LOOPBACK cntrol words are "010", which means they work in PMA mode ,both tiles work perfectly, but when the LOOPBACK cntrol words become "000", which means they work normally, tile0's signal "port_initialized" stay "0" all the time, that means the rocketio_wrapper hasn't been initialized, however, tile1 works correctly.
So, why the tiles work differently, and how to deal with this situation.
Very thank you!
02-03-2010 07:31 AM
I'm using the same LV155T chip for SRIO and MGT 156, but haven't made it this far yet to help you. If you help me get mine going then I can catch up with you and maybe both of us can help each other out. I need to know if the CORE works right out of the box or if it needs to be initialized in a certain way to be ready to communicate with DSK board. TI c6482. I am just setting the CARs and CSR registers that I can modify and then hopefully am ready to try to communicate with DSP. Anything else on FPGA side that has to be done to be ready?