Connectivity

[smillertait]

Hi,

I am using a Spartan 6 LX150, ISE 13.1 and I have a question regarding the jitter calculation performed by the Clock Generator Wizard.

I am using the wizard to ensure that the oscillator I wish to use as the input to the PLL will allow the PLL to produce a sufficiently low jitter output to be used as the clock for a MCB configured for DDR3.

However, even when I put in "ideal" settings (i.e. lowest input jitter the tool will allow), I cannot get the output jitter below approx 110 - 130ps, which violates the requirements of the DDR3 IC I am using. However, I know that this IC should work, as it is used on the Xilinx development boards.

Is there something that I am missing or misunderstanding here? Or does the MCB reduce jitter on the clock it receives from the PLL?

Any clarification/assisstance would be greatly appreciated.

Thanks

[rcingham]

What is the jitter spec. for the oscillator on the Xilinx development board(s)? Can you use an oscillator that is at least as good?

[smillertait]

Thanks for the suggestion. Jitter specifications for the oscillator used on the SP605 board are:

RMS Phase Jitter (random) = 0.7ps typical
RMS Period Jitter = 2.4ps typical, 3.5ps maximum

(From: http://www.sitime.com/products/datasheets/sit9102/SiT9102LF_Rev1.44_05-12-2010.pdf)

I could probably find something similar to that and use it on my board, however it is still a bit frustrating to not be able to understand how to get a proper estimate with the tools. Also, since my PLL settings will be different than on the development board, I assume I might get different jitter performance (although I'm guessing this is a small risk).