Connectivity

[syuan523]

Hi all,
Hope to get some guidance here.

Target device is the Virtex-5 LXT. I'm trying to build two independent Aurora links on one GTP tile. Independent meaning the two links will have to start/stop transmitting separate data streams individually. Data rate, clocks, resets, etc. can be the same.

I opened a webcase with Xilinx. But this is not one of the supported modes of operation of the GTP, they can not provide any guidance. The applicantion engineer told me that he heard about other customers that have done something similar, and he believes that they’ve got it working.

Any help will be appreciated,

Scott

[mcgett]

While you can do this, providing that you use the same reference clock for each Aurora link, this is not a feature in the CoreGen Aurora LogiCore module and there are no plans to implement an enhancement to support this.

If you want to do this you will have to do this yourself.

[syuan523]

Just curious, is there a reason why this mode of operation is not supported?

[mcgett]

It is a combination of a lack of demand, no one else had made request for this until your post that I am aware of, and available engineering resources.

Ed

[aleclair]

I want to do the exact same thing with a V5 SX50T!  I have designed an entire architecure based on the fact that this should be flat out simple.  Has anyone gotten this to work?  Is it possible to send the same exact data out both Aurora links on one GTP tile?

[kaitokid]

1. Create two Aurora projects using CoreGen.

2. Combine them into one design.

This is what I can think about. But I haven't tried.

You may try it and if you meet any difficulty, you can post it. We can discuss.

[aleclair]

Hi Scott,

I am checking with my local FAE to see if we can do what you want.  Perhaps my FAE will have a different path into the factory that will give us a better answer.  I already know that I can send identical data on two links from one Aurora core.

Aaron

[saikey]

It shouldn't be terribly difficult.  Mostly just alot of typing.

Just add the extra data and status ports to the top aurora module.

Then inside the top aurora module create a second instantiation of each lower level module, and connect to the previously unused half of the GTP.

I imagine that the biggest problem will be meeting timing, depending on the structure of the rest of your design.

It would be more difficult if you were looking for different data rates on the two Aurora channels.  Which could be accomplished, assuming that the data rates were multiples that the GTP internal PLL would support.

-Shawn

[timdavis@aspenlogic.com]

I needed this capability as well. The AVNET AES-XLX-V5SXT-PCIE95-G development board has two SFP interfaces which connect to a single GTP_DUAL instance. Each SFP connected to a fiber going to seperate destinations. Since the PCB wiring is fixed I was stuck trying to implement a solution using the existing Aurora code generated by coregen. While not logically difficult the janitorial engineering was error prone. It took me quite a while to get the two links up in simulation. Extracting the GTP_DUAL and bringing it up to the top level was not easy.

Based on the desire to support the AVNET card I would highly encourage Xilinx to support this capability in Coregen.

[lbeardsley1]

My company has implemented this functionality.  It was painful and we incurred a lot of NRE to be able to accomplish it.  We have heard from our FAE that so many people are requesting that it will soon be part of the Architecture wizard.