Error with dual microblaze processor design on virtex5 xc5vlx110t board.

mshiv002 · ‎02-08-2010

Hi,

I am referring dual processor reference design suite XAPP996.pdf, where in I am working on dual microblaze system with shared memory project. When I download the design suite file and update bitstream with xilinx platform studio for XC5VLX110T board I get the following error. I would really appreciate if someone could help me in figuring out the error.

Also please help me out in finding the usage document of delay controller.

ERROR:Place:872 - Delay element
   "DDR2_SDRAM_32Mx32/DDR2_SDRAM_32Mx32/mpmc_core_0/gen_v5_ddr2_phy.mpmc_phy_if_0/u_phy_io_0/gen_dq[42].u_iob_dq/u_idela
   y_dq" has been placed at IODELAY_X0Y245 due to the following location constraint on component
   "fpga_0_DDR2_SDRAM_32Mx32_DDR2_DQ<42>":
   COMP "fpga_0_DDR2_SDRAM_32Mx32_DDR2_DQ<42>" LOCATE = SITE "N24" LEVEL 1
   However, the delay controller that calibrates this delay element has not been used. Please instantiate a delay
   controller and apply appropriate location constraint, or instantiate one delay controller for the design with out any
   location constraint. Please refer to the usage document to use the controller efficiently.

Thanks and Regards,

Mohan

iulian.nita@upb.ro · ‎06-24-2010

Hello,

I had the same problem and i couldn't resolve it. I created a new BSB dual-processor design for my board and modified the software file code. You want I can share you this project. ( I use EDK 11.5)

Also you need the board support package for your FPGA ( i supposed you have XUPV5 from Digilent). Do you have it ?

Fill free to contact me if you have any question !

Iulian

mshiv002 · ‎02-08-2010

Hi Iulian,

Thank you so much for your reply and please do send me the source code you are using. I will try if I can solve my problem. I have a board support package.

Regards,

Mohan