Hello Xilinx Community :)
I am a university student studying Mechatronics Engineering and I have recently been given a job at a small high frequency trading company. My long term task is to improve performance of the intake of market data using an fpga. The intake method into the fpga is via ethernet and from the fpga to the computer is via PCIe.
I am starting off small, with an sp605 dev board to get started. I have decided to start off with the ethernet side of things and once I get something working, go onto PCIe. I have been working on this for about a month now, slowly learning more and more about Xilinx tools, verilog, ethernet protocol, IP cores etc. My previous experience with fpga's was just one digital circuitry paper at university, which involved the use of verilog, creating a simple calculator on an (alterra) board. So most of this stuff is new to me.
I started off by ripping apart the Base Reference Design for the board and extracting all the things that have to do with ethernet (ethernet MAC, mdio interface etc) in an attempt to try make my own project/design. The goal is to simply receive data and light up the LED's on the board with the receiving stream. I managed to get the ethernet lights next to the ethernet port blinking when i send it some data, and managed to obtain a link speed. But i did not manage to receive any visible data.
The approach im taking now is to use the free Ethernet 1000BASE-X PCS/PMA or SGMII core to receive data which seemed to be a simple solution. I tried setting up the core in SGMII mode to create the SGMII to GMII bridge. I have tried to configure the core with the mdio/auto negotiation and hook it up to the MAC i took from the BRD design. With this the status vector shows me that i am receiving invalid data and that the data received is not in the look up tables (at least im getting some sort of feedback).
I also tried configuring the core without the mdio interface or auto negotiation, but with this i get no feedback from the status vector. I have been going through the core user guide and datasheet, following what it tells me to do (e.g. tie the signal detect high, set the configuration vector properly). However I cannot manage to establish a link, and I have run out of ideas. I am using the example design it provides and integrating into it.
Am I missing something fundamental? Do I have to connect some things to the FPGA PHY pins (e.g. PHY_RXD[7:0]) or make any other constraints in the UCF? I am expecting to receive incoming data from the core and simply displaying it on the LED's as it comes in. Is this expecting too much?
Any advice on simple steps to use this core/cores in general would be appreciated.
Thank you
Mario
p.s. I'm using this ethernet packet generator to send the board packets directly from my computer: http://eth.cyberine.com/
