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Contributor
barco2
Posts: 35
Registered: ‎02-13-2009
0

GTX PLL reset problems at low die temperature

Hi,

 

I have a problem with a Virtex6 GTX transceiver design regarding the PLL lock after reset.

 

My design uses a 125MHz refclk for the rx_pll. TX and RX are both clocked by the rx_pll and are running at a line rate of 5Gbps. TXOUTCLK ist at 250MHz. This is fed via a BUFG to a MMCM. RXUSRCLK and TXUSRCLK use a 250MHz clock from the MMCM (via BUFG). RXUSRCLK2 and TXUSRCLK2 use a 125MHz clock from the MMCM (via BUFG). RX_DATA_WIDTH and TX_DATA_WIDTH are set to 40.

 

Now, my problem is, the TXOUTCLK is not running when the transceiver is reset at a die temperature below 60C. RXPLLLKDET is high, even though there is no TXOUTCLK running. But when the temperature is above 60C everything works fine.

 

Does anyone have an idea what's wrong here?

 

Regards

Martin

Newbie
cobi
Posts: 1
Registered: ‎11-06-2009
0

Re: GTX PLL reset problems at low die temperature

Contributor
barco2
Posts: 35
Registered: ‎02-13-2009
0

Re: GTX PLL reset problems at low die temperature

[ Edited ]

Thanks Cobi,

 

I know this AR. But I think my design is not affected by this problem since I have set TXPLL_DIVSEL_OUT=1.

However, I will try whether this double-reset sequence also fixes my problem. This was #1 on my more-things-to-try-list.

 

Regards

Martin

 

Update: Just tried this on hardware, no change in reset behavior, still fails below 60C.

Expert Contributor
rcingham
Posts: 2,010
Registered: ‎09-09-2010
0

Re: GTX PLL reset problems at low die temperature

60 celcius is NOT a low die temperature, more like medium!

------------------------------------------
"If it don't work in simulation, it won't work on the board."
Contributor
barco2
Posts: 35
Registered: ‎02-13-2009
0

Re: GTX PLL reset problems at low die temperature


rcingham wrote:
60 celcius is NOT a low die temperature, more like medium!

Well, you are right, but this does not help me solve my problem. With passive cooling my FPGA is at 70C, with active fan cooling it runs at 50C. And yes, I'd prefer being able to run the device at 50C. But this does not work with my current transceiver instatiation and I still don't have a clue where to search for the problem.

 

Next thing I am going to try is connecting a better reference clock. Currently I am using the 125MHz ICS844021I on the ML605 board for my 5G transceiver, this might be somewhat suboptimal.

 

Martin

Xilinx Employee
gguasti
Posts: 135
Registered: ‎11-29-2007
0

Re: GTX PLL reset problems at low die temperature

hello,

please, are the *USRCLK* still toggling during reset or are they static too?

When comparing oscillators you could find useful AR38506.

best regards,

GG

Contributor
barco2
Posts: 35
Registered: ‎02-13-2009
0

Re: GTX PLL reset problems at low die temperature

Hi Giovanni,

 

the *USRCLK* signals are not toggling, because they are generated by an MMCM which is fed from TXOUTCLK.

FYI, I opened webcase #915096 which is handled by John Heslip now.

 

Thanks

Martin