06-07-2012 11:03 PM
I'm working on a Virtex 6 design that uses the AXI Ethernet IP for gigabit network communication through an SFP module. The 125MHz low jitter reference clock needed for GTX gigabit operation is not available until after the FPGA has powered up, configured, and then sent configuration instructions to an external PLL that generates the 125MHz clock. How do I hold the GTX transceivers in reset until that clock is ready? I don't see an available port for the AXI Ethernet core that appears related to the GTX PLL reset. Would holding the entire Microblaze system in reset do the trick, or am I missing something obvious?
06-08-2012 02:39 AM
Don't have AXI Ethernet IP experience, but:
If it outputs no clock, the GTX won't do anything, but holding in reset sounds like a good idea.
If some other frequency, then it will not correctly receive any Ethernet packets that arrive, possibly setting an internal error flag that needs clearing as part of the initialisation routine.
"If it don't work in simulation, it won't work on the board."
06-08-2012 09:39 PM
False alarm. It turns out the 2.5V supply was running near its 1A current limit, and adding in the GTX transceiver pushed it over. I changed the limit to 2A, and all is well. I am still curious about how to hold the GTX PLL in reset in an XPS project.