03-03-2009 11:00 AM
How to assign Ethernet MAC address without using EDK?
I’m using LogicCore “Virtex5 Embedded Tri-mode Ethernet MAC Wrapper” to generate SGMII for Virtex5FXT. There is an “Ethernet MAC Example Design” for a real hardware test environment.
My questions is:
How to assign MAC address for this example without using EDK?Thanks in advance
03-03-2009 07:27 PM
You don't really need to "assign" MAC address to the core. When you send a packet, you put the MAC addresses (DA and SA) in the transmit data.
05-07-2009 08:25 AM
I use the IP Virtex5 Embedded Tri-mode Ethernet MAC Wrapper” for the Virtex 5 FX130T on the ML510 board.
I use the top file "example_design" from Xilinx and I added a block which sends permanently Ethernet frames as follows : Mac addresses (DA and SA), protocol type and data.
But that's no ethernet frames on wireshark and the Tx led doesn't blink !!
Have you got a working firmware for this ethernet part on ML510 that I could use and without EDK ?
Thanks in advance
06-19-2012 07:35 AM
I implemented the example design of Virtex-5 Embedded Tri-Mode Ethernet MAC Wrapper v1.8 on ML505 board.
I generated the example design files from Core Generator version 14.1.
Then, I imported this files to ISE 14.1 in order to check syntax, implement the design and generate the programming file. Finally, I downloaded the design to ML505 board, but I noticed that the TX LED never light in spite of I connected the board directly to a Computer and send IP packets toward the board. Also, I didn't get any packet on wireshark.
What can I do in order to fix this problem.
06-21-2012 05:42 AM
Don't forget you probably have to modify the example design and add a reset signal do drive the reset signal to the PHY, if necessary.
And verify you clock settings, depending on what configuration you are using (MII/GMII/SGMII), you might have many different clocks. Be sure you are asserting then correctly on the .UCF file.
Also, don't forget you need a stable 200MHz clock source for the REFCLK signal, which is used by the IOBDELAY elements.