IEEE 488 GPIB

forte31 · ‎02-06-2008

Does Xilinx have a solution or design approach for an IEEE-488 interface?

austin · ‎02-27-2008

f,

Apparently not (too old). National Instruments still has GPIB controllers, and they use Xilinx FPGA devices, so perhaps they have developed the VHDL/verilog to do it, but they are not in the business of selling their imtellectual property.

Maybve there is some open core design out there. As I said, that is pretty old stuff, and once something has been relapced by some newer standard, it is unlikely that it is of much value any longer, so it 'goes away.'

Austin Lesea
Principal Engineer
Xilinx San Jose

bassman59 · ‎02-25-2008

forte31 wrote:

Does Xilinx have a solution or design approach for an IEEE-488 interface?

See here: http://www.interfacebus.com/Design_Connector_GPIB.html

It's a VERY slow (by modern standards) half-duplex parallel bus that uses LSTTL logic levels. The biggest issue is that you may have a device which has output swings beyond what the 3.3V rail the modern FPGAs support. But since GPIB is so slow, a level translator between the bus connector and the FPGA is a reasonable thing to use.

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