I am using the example design for Gigabit TEMAC 4.4 on spartan 6 LX150T board. The problem that I am facing at the moment is that I am able to get the on board National PHY to respond when receiving packets from the LAN. The packet data passes through the entire RX section ( gmii_interface module, TEMAC Core rx side , rx fifo , address swap module ) and back to TEMAC and onto the gmii_interface. On the wire I have the gmii_txd (with the DA and SA swapped), txd_data valid signal (high for the duration that the packet is being sent) and txd_err signal (low through out i.e no error). I am not able to check the gmii_tx_clk on chipscope. This clock is generated by an ODDR2 component inside the gmii_interface module.
So the question I have is, can the gmii_tx_clk be the issue? Any other ideas of what I can try. I may point out that I got the same results when trying out with a spartan3 custom board using the same National PHY.
regards
Umar
