Connectivity

[golson]

Hi What should we do with unused GTX pins.  I searched the forums and found that someone said

the GTX was being optimized out because he did not connect some or all of his GTX Inputs and outputs.

I have the same situation, I have a board that has a GTX that has no Inputs or outputs hooked up.  And I need

the clock to be forwarded to other GTXs in the line.  If I do not hook up RX and TX to pads will the GTX be optimized

out by Map. 

Also, should GTX RX pins be allowed to float if they are not used?  Or pulled up or pulled down?

Thank You,

  Gary

[rcingham]

> Also, should GTX RX pins be allowed to float if they are not used? Or pulled up or pulled down?

We ground them. Seems to be ok.

[golson]

Hi rcingham,

Thank you for that information.  The unused gtx is being optimized out if I don't place the unused GTX RX and TX pins

onto PADs.  Is this the correct procedure?

Thank You,

  Gary

[mcgett]

The software should just handle everything correctly if you have a REFCLK that has a destination that is a not in the same location.  There is no need to instantiate an unused GTX in your design.

[golson]

Hi Mcgett,

  In Core Generator II selected four GTXs that are adjacent to each other and created a Core.  I took the example design

and commented out the chipscope and VIOs from the design.  Placed the Design into my Main design. 

The one GTX that is unused is between two others that is used.  If I add ports to my design so that the TX and RX

are wired to PADs the software does not error.  But if I don't do that then the software can not find the inused GTX.

I think mapping is removing that GTX during optimization. 

Gary

[mcgett]

Can you please provide more specifics on you design? Which device/package? Which GTX locations are actively used by your design? Which pins are used by the reference clock?

[golson]

Hi Mcgett,

   I am targeting the chip used on the ML510 board 130T.

I just include the following file I attached to my ISE project.

I also have another question about the extra PLL the top level file includes.  I have run out of PLLs.  I have

6 on the FPGA(PLL_ADV).  I include 4 GTX groups (or individual dual Tiles)  and need to include one more

GTP dual Tile.  Unfortunately I have now run out of PLLs.  I tried the DCM_ADV one time ( a week or two ago) and It errored out

saying something about two things driving the same net.

This is HD-SDI choice that I made.  Do I need to use these general PLLs or can the Internal PLLs (Shared PMA PLL)

provide the clocks I need.  Saving my device from loosing all of the Clock resources I have.

Thank You,

  Gary