Connectivity

[woody242]

All,

I am working on getting the Marvell Phy working in RGMII mode on the ML405 dev board.  I am using V10.1 of the EDK and V1.01b of the XPS_LL_TEMAC.

I have all the constraints per the manual in the ucf file.  The following two lines cause a failure when generating the bitstream

# RGMII Spec: 1ns setup 1ns hold, DDR
INST "rgmii_rxd_0<?>" TNM = "rgmii_rx_0";
INST "rgmii_rx_ctl_0" TNM = "rgmii_rx_0";

I get a failure indicating that 

ERROR:ConstraintSystem:58 - Constraint <INST "rgmii_rxd_0<?>" TNM =
   "rgmii_rx_0";> [system.ucf(343)]: INST "rgmii_rxd_0<?>" does not match any
   design objects.

ERROR:ConstraintSystem:59 - Constraint <INST "rgmii_rx_ctl_0" TNM =
   "rgmii_rx_0";> [system.ucf(344)]: INST "rgmii_rx_ctl_0" not found.  Please
   verify that:
   1. The specified design element actually exists in the original design.
   2. The specified object is spelled correctly in the constraint source file.

Has anyone else encountered this.  These lines appear to be in every example of constraints for RGMII

My constraints per the XPS_LL_TEMAC are 

#EMAC0 TX Client Clock
NET      "*/tx_client_clk_in_0*"  TNM_NET   = "clk_client_tx0";
TIMEGRP  "rgmii_client_clk_tx0"             = "clk_client_tx0";
TIMESPEC "TS_rgmii_client_clk_tx0"          = PERIOD "rgmii_client_clk_tx0" 7800 ps HIGH 50 %;

#EMAC0 RX Client Clock  
NET      "*/rx_client_clk_in_0*"  TNM_NET   = "clk_client_rx0";
TIMEGRP  "rgmii_client_clk_rx0"             = "clk_client_rx0";
TIMESPEC "TS_rgmii_client_clk_rx0"          = PERIOD "rgmii_client_clk_rx0" 7800 ps HIGH 50 %;

#EMAC0 TX PHY Clock
NET      "*tx_gmii_mii_clk_out_0*"  TNM_NET = "clk_phy_tx0";
TIMEGRP  "rgmii_phy_clk_tx0"                = "clk_phy_tx0";
TIMESPEC "TS_rgmii_phy_clk_tx0"             = PERIOD "rgmii_phy_clk_tx0" 7200 ps HIGH 50 %;

#EMAC0 RX PHY Clock
NET      "*rgmii_rxc_0*"  TNM_NET           = "clk_phy_rx0";
TIMEGRP  "rgmii_clk_phy_rx0"                = "clk_phy_rx0";
TIMESPEC "TS_rgmii_clk_phy_rx0"             = PERIOD "rgmii_clk_phy_rx0" 7200 ps HIGH 50 %;

#Set the IDELAY values on the data inputs
# modify to suit your design
INST "*rgmii_rx_ctl_delay"      IOBDELAY_TYPE = FIXED;
INST "*rgmii_rxd?_delay"        IOBDELAY_TYPE = FIXED;
INST "*rgmii_rx_clk_?_delay"    IOBDELAY_TYPE = FIXED;

INST "*rgmii_rx_ctl_delay"      IOBDELAY_VALUE = 0;
INST "*rgmii_rxd?_delay"        IOBDELAY_VALUE = 0;
INST "*rgmii_rx_clk_?_delay"    IOBDELAY_VALUE = 36;

# RGMII Spec: 1ns setup 1ns hold, DDR
INST "rgmii_rxd_0<?>" TNM = "rgmii_rx_0";
INST "rgmii_rx_ctl_0" TNM = "rgmii_rx_0";

TIMEGRP "rgmii_rx_0" OFFSET = IN -7 ns VALID 2 ns BEFORE "*/RGMII_RXC_0" LOW;

# Timing constraints for IDDR/ODDR paths
INST "*rgmii_rxd?_iddr"         TNM = "rgmii_iddr";
INST "*rgmii_rx_ctl_iddr"       TNM = "rgmii_iddr";
INST "*rgmii_txd?_oddr"         TNM = "rgmii_oddr";
INST "*rgmii_tx_ctl_oddr"       TNM = "rgmii_oddr";
INST "*v4_emac"                 TNM = "emac";

NET "*rgmii_rx_ctl_falling_?_i" TPTHRU = "inpath";
NET "*rgmii_rxd_falling_?_i<?>" TPTHRU = "inpath";
NET "*rgmii_txd_falling_?_i<?>" TPTHRU = "outpath";
NET "*rgmii_tx_ctl_falling_?_i" TPTHRU = "outpath";
NET "*rgmii_tx_ctl_rising_?_i"  TPTHRU = "outpath";

TIMESPEC "TSin" = FROM "rgmii_iddr" THRU "inpath" TO "emac" 7200 ps DATAPATHONLY;
TIMESPEC "TSout" = FROM "emac" THRU "outpath" TO "rgmii_oddr" 7200 ps DATAPATHONLY;

# Need to TIG between the LocalLink clock and the rx_client and tx_client clocks
NET "*/LlinkTemac0_CLK*" TNM_NET = "LLCLK0";

TIMESPEC "TS_LL_CLK0_2_RX_CLIENT_CLK0"  = FROM LLCLK0 TO clk_client_rx0 8000 ps DATAPATHONLY;
TIMESPEC "TS_LL_CLK0_2_TX_CLIENT_CLK0"  = FROM LLCLK0 TO clk_client_tx0 8000 ps DATAPATHONLY;
TIMESPEC "TS_RX_CLIENT_CLK0_2_LL_CLK0"  = FROM clk_client_rx0 TO LLCLK0 8000 ps DATAPATHONLY;
TIMESPEC "TS_TX_CLIENT_CLK0_2_LL_CLK0"  = FROM clk_client_tx0 TO LLCLK0 8000 ps DATAPATHONLY;
# end RGMII

Thanks,

John

[gszakacs]

Since the two offending lines are the only ones without a leading "*" wildcard character,

I'm guessing these instance names are not from the top level of your hierarchy.  Try

adding a leading */ like:

INST "*/rgmii_rxd_0<?>" TNM = "rgmii_rx_0";
INST "*/rgmii_rx_ctl_0" TNM = "rgmii_rx_0";

HTH,

Gabor

[woody242]

Thanks Gabor,

Unfortunatley, I get the same error if I put just an * or an */ in those lines.

These appear to be the signals of interest in the top level of the V1.3 RGMII Wrapper

      RGMII_TXD_0                     : out std_logic_vector(3 downto 0);
      RGMII_TX_CTL_0                  : out std_logic;
      RGMII_TXC_0                     : out std_logic;
      RGMII_RXD_0                     : in  std_logic_vector(3 downto 0);
      RGMII_RX_CTL_0                  : in  std_logic;
      RGMII_RXC_0                     : in  std_logic;

John 

[gszakacs]

John,

If these are actually pins, i.e. top level ports, they should work without the "*"

Did you try to comment out the offending lines in the .ucf file and see if the

names have changed in the translated design?  Also did you try to use

uppercase names in the .ucf file in case this is one place where the

tools become case-sensitive?

All I can think of...

Regards,

Gabor

[woody242]

Those signals are not pins, rather they are PORT definitions in the EDK mhs file.  Is it possible that they are taking on the name of the signal that I use to connect them to the external port definition in the mhs? 

I did get one to match by the following...

INST "*rgmii_rx_ctl_0*" TNM = "rgmii_rx_0";

I added * at the end which I noticed in some net definitions.  I am new to the Xilinx constraints so I am not sure what effect this will have.  I am going to try using my signal names from the mhs and see if they match.

John

[woody242]

Oh yes, I did try case matching both upper and lower.  No luck.

[woody242]

Hi Gabor,

What file would I look in to see the translated design?

Thanks,

John

[ywu]

In your project directory, there is a sub-directory called "hdl". Open it and look for a VHDL file called "system.vhd" assuming that your EDK project name. Open the top level VHDL file and you shoud see the external port names.

Cheers,

Jim

[woody242]

Hi Jim,

Thanks,  I looked at the system.vhd file and saw that the two signals that I got the errors seemed to be defined in the Temac Wrapper.  Specifically...

      RGMII_RXD_0 : in std_logic_vector(3 downto 0);
      RGMII_RX_CTL_0 : in std_logic;

The two constraints were only accepted when I used the port definitions at the top level system definition...

    fpga_0_TriMode_MAC_GMII_RGMII_RX_CTL_0_pin : in std_logic;
    fpga_0_TriMode_MAC_GMII_RGMII_RXC_0_pin : in std_logic

Now my design is failing timing but at least it progressed further.  I assume that the intermediate signals are optimized out prior to the constraints being applied?

John

[woody242]

Sorry bad cut and past the seconds group of signals should have been...

    fpga_0_TriMode_MAC_GMII_RGMII_RXD_0_pin : in std_logic_vector(3 downto 0);
    fpga_0_TriMode_MAC_GMII_RGMII_RX_CTL_0_pin : in std_logic;

By the way in my system.mhs I had the following signals defined to connect the pin ports to the temac...

  signal fpga_0_TriMode_MAC_GMII_RGMII_RXD_0 : std_logic_vector(3 downto 0);
  signal fpga_0_TriMode_MAC_GMII_RGMII_RX_CTL_0 : std_logic;