When RXUSRCLK is sourced by TXOUtCLK+BUFG,the GTX works normally. However, when When RXUSRCLK is sourced by RXRECCLK+BUFG,the GTX does not work well. In the configuration, he clock correction is used, and TX/RX buffer is also used. My question is why RXUSRCLK can not be sourced by RXRECCLK+BUFG?
When RXUSRCLK is sourced by RXRECCLK+BUFG, the RX side of GTX can not properly receive data ( part of FC core 3.3). However, it works during simulation.
Is it necessary to present the parameter configuration of GTX?
CDR takes reference of the serial clock generated by PLL and recovers the clock based on the transitions in the incoming data. So, the stability of the RXRECCLK depends on the amount of toggling in the receive data and the quality of the REFCLK given to the PLL. By quality of the REFCLK, I mean the amount of jitter in the REFCLK input should be less.
If there is any jitter on the REFCLK it can translate to RXRECCLK.
I try the case. REFCLKOUT of GTX drives the DCM, whose ouput clock (+BUFG) drives RXRECCLK. It works. Does it mean the amount of jitter in the REFCLK input is less?
