02-09-2011 01:54 PM
Desired application: RapidIO v5.5 core through coregen on XC6SLX100T interfacing to 4 rx/tx mgt pairs.
System interconnect: An example topology of five boards would be one master controller board (with XC6SLX100T) connecting to four secondary controller boards (each with XC6SLX100T). The master would use 1 rx/tx pair to communicate with one secondary (i.e. 4 master rx/tx pairs talk to 4 secondary boards).
Question: For the master controller board, I do not want channel bonding enabled as each rx/tx pair must be completely independent. Can I generate a 4x RapidIO core and somehow disable channel bonding? Or, should I instead generate 4 separate 1x RapidIO logical/transport cores and tie them all to 1 PHY?
I have started wading through RapidIO v5.5. documentation; however, it seems that there is only 1x mode or channel-bonded 4x mode. Can someone point me to an app note that describes my particular application?
02-10-2011 10:29 AM
You will have to create 4 x1 cores.
You can't connect a x4 core with x1 cores, which is what it sounds like you are trying to do.
A x1 core will send different synchronisation data then a x4 core. It's not that the synchronisation data of 4 x1 cores add up to be the same as 1 x4 core.
So both the x4 core as well as the x1 core won't be able to link up in this way.
05-03-2012 10:30 AM
I have some problems with core serial RapidIO on Spartan-6. How many hard blocks have S6 silicon? According to srio_ds696 4 blocks, but the second page of datasheet says only about x1 configuration. Why? Does it mean that I can use each of this four hardware blocks separately and I should generate core for each of them? (in hypathetical project). But I want to use one core with 4 lanes. Can I do this with Spartan6?
Sorry for my english.