06-13-2012 10:27 AM - edited 06-13-2012 10:35 AM
I am getting this error after changing the MGT PLL (PLL_ADV) to a DCM_ADV.
ERROR:NgdBuild:455 - logical net 'GT124_TP/tile0_txoutclk0_i' has multiple
pin TXOUTCLK0 on block GT124_TP/gt124_i/tile0_gt124_i/gtx_dual_i with type
pin PAD on block GT124_TP/tile0_txoutclk0_i with type PAD
It suggests that the tile_0_txoutclk0_i hookup is causing a multiple driver error. I do not see a reason for this
error. I just swapped out the PLL with a DCM and hooked it up.
I have attached the code to see.
Solved! Go to Solution.
06-13-2012 11:05 AM
I am confused: the MGT PLL is not something you can 'replace' it is built into the MGT and part of it.
Whereas the DCM is something else, and the PLL in the clock management tile, is something else, again.
So what are you trying to do (and why)?
Xilinx San Jose
06-13-2012 11:35 AM - edited 06-13-2012 11:37 AM
I am trying to use the Example design given by the GTX wizard in my design. I actually added about 2 groups and two individual
GTX designs to my design. But Each time I add a wizard generated design to my ISE project one of the General PLLs is used up. And It is using 6 out of 6 PLLs in my design. I am using the 130 part same part as used in the ML501 board. There are
more DCMs available so I was trying to use these for another GTX I wanted to add.
I was hoping that the Example design would use the MGTPLL. and not the General PLLs. But It seems to be using the General PLLs for the usrclocks.
Perhaps I should have included the GTX Attributes into the UCF file?
06-13-2012 05:44 PM - edited 06-13-2012 05:46 PM
I got DCM to work after I changed from Default setting CLKIN external to CLKIN internal.
By doing this the DCM input will not have a BUFG inside the DCM block. Hence it will look similar to the "MGTPLL" which does not have a bufg on the clkin internal to PLL block.
The MGTPLL actually turns out to use up a general PLL. I wish I new a way to get the internal PLL to perform this function
and save a DCM or a PLL.