Connectivity

[zoujx2008]

Hi,

I am using the rocket IO to do the data transmitting job between two XC5VSX50Ts. The system is composed by a daughter board and a mother board, the XC5VSX50T of the daughter board transfer the ADC data to the mother board by rocket IO through the Samtec high speed board to board connector.

I want to verify the connectivity of the rocket IO first. So, I burn the IBERT core (1Gsps line rate)  into the two FPGAs, and using the PBRS31 and there is no err counts.

But when I generate the rocket IO core using the IP core wizard, then implement the example design into the two FPGAs, And find there is some err counts observed in the ILA core. And I don't know what the problem it is. May be the incorrect  parameter setting during the rocket IO core generation?

So, which result should I trust? The IBERT core testing result or the latter one? And what reason may cause two different results?

thank you very much

[zoujx2008]

I find out the reason cause the check err is the occasional one byte missing in the 16 bits rxdata in the example design implementation. A snapshot is attached. In the snapshot, the "1B" is missing 6 clock cycles before the err counts increase.

I think it is not caused by the signal integrate problems. Is it caused by the unproper setting of the elastic buffer? The RXBUFSTATUS1[2:0] is always "010" which means " Number of bytes in buffer is greater than CLK_COR_MAX_LAT", is it correct? Shouldn't it be "000" for nominal condition? Is this the reason causes the check err of  example design? How can I fix it?

Thank you very much

[gguasti]

Hello V5 user,
IBERT tells you do not have SI issues.
At the RX side IBERT uses the recovered clock to clock the logic. Thus if the CDR is well locked to data you do not see buffer errors.

Maybe in your design you are using the RX local oscillator to clock the RX logic? maybe you do not have the clock correction active, or the CC word density does not allow a good compensation for ppm difference between TX and RX oscillators?

In a debug I would first try to answer to the following questions:
1) what is the max ppm in my system? (i.e. if the TX oscillator has max 50ppm and RX oscillator has max 20ppm, your design needs to compensate for 70ppm)
2) is the CC able to compensate for the ppm? (i.e. what is the CC word density in your data stream?)
3) is my signal rich in transitions? this helps the CDR
4) compare IBERT and your design CDR setup
5) does a RX buffer reset fix the problem?
6) does a sinchronous design fix the problem? please try alternatively both, use RX recovered clock to clock the RX logic and RXUSRCLK; use the same oscillator to clock the TX and RX.

Best regards,
Giovanni

[zoujx2008]

Hi,Giovanni

Thank you for the reply. I have tried to use the CLKREC to generate rxusrclk0 and rxusrclk20. Then the buffer err was gone. But I want to use the local oscillator to clock the RX logic, and the local oscillator has the same frequency as the TX reference oscillator, but the phase relationship is unknown. So, it is must be the inappropriate clock correction problem. But I don't know how to do the clock correction right...Is there any user guide or xapp doc which can help me out?

Thanks very much. 

Regards

Jianxiong Zou