I want to check the design integrity of pcb traces between a Virtex 6 and a Spartan 6 XC6SLX45T. I'd prefer not to do an HDL protocol design in the S6 so it doesn't become part of the integrity question. I'm thinking I can create an IBERT in the appropriate bank of the V6 part, and do a "wraparound" in the S6 GTP. I'm looking for suggestions as to a best approach. Looking at the S6 it looks like I can do a far end pma loop back? If so can I do this from the GTP wizzard?
You can test this setup in two ways. 1. Generate IBERT design on spartan-6 also and select far-end PMA/PCS loopback in the GUI 2. Generate the GTP wrapper from gtp wizard and set the loopback signal in <component_name>_exdes.v/vhd according to the settings required for far-end pma/pcs loopback.
It looks like the far end PMA is sipo to piso? If so, I would assume the ref clock must be correct also and same frequency as the V6 source? Looking at the data, it doesn't look like there is any way to loop back PMA reciever to PMA transmitter, correct?
