07-09-2012 05:32 PM - edited 07-10-2012 11:43 AM
I am trying to implement a 10G MAC/XAUI design on a Virtex 5 FX200T FPGA. I have tested the same design on a V5 LX100T FPGA successfully and have now generated appropriate MAC/XAUI cores for the the FX200T FPGA. The issue I am seeing now is that data is being sent out of the MAC into the XAUI block, but the XAUI core does not seem to be sending data over a CX4 cable connected to another identical board.
- Using XAUI v10.1, ISE 14.1
- Hitech Global HTG-V5-PCIE-200-2 development board with a CX4 adapter (user-manual attached).
- Using GTX tiles 116 and 120
- Fowarding reference clock from GTX 124 (powered down) to GTX 116 and 120
- Able to confirm the following on chipscope: align_status = '1', sync_status = "1111", mgt_tx_ready = '1', mgt_rxlock = '1', and all clocks in the design are active
I have used iBERT to check the transcievers and see no bit errors in near-end PCS and PMA loopback modes. However, when the loopback mode is set to none on one card and set to far-end PMA/PCS on another card, there are continuous bit-errors. The link remains high throughout. I am not sure if there are any settings in the transceiver that I need to modify.
Appreciate any help.
07-11-2012 01:32 PM
How are you checking that there is no data is getting sent over the CX4 cable to the other board? Is it that on the link partner no data frames are recieved? Or are idles not received either? Does the XAUI link partner on the other board ever see align_status or sync_status go high?
If you do near end loopback on the board that you are having tx problems with does sync and align status go high on the rx? Are you able to receive data frames?
You mention having two identical boards. Are they both behaving the same?