Connectivity

[awdelp]

Hi,

Recently ive been working on a program that will display numbers on a seven segment led.  I originally started this on the Xilinx ML505 evaluation board, and was able to create it successfully.  However, this is a minor first step of the project I am working on which actually requires a different board that I created.  Through suggestions from people who have put together boards that are similar to mine we wired a 80 MHZ oscillator to the MGT clock pins on a Virtex 5 lx50t 1136 pin.  My question is in regards to how you would go about obtaining the clock to be used in another program (the display program).  

I have already tried to stick both of the differential clock signals through an IBUFDS which then went to a clkin input off a GTP transeiver.  Then I took the REFCLKOUT to be used in my display program.  However, I do not seem to be able to get a signal from this.

Any help would be greatly appreciated.

Albert

[mcgett]

The MGT REFCLK pins are intended for use by the MGT in the device.  While it is possible to get the clock propogated to the fabric, it isn't an easy or clean solution.  Your task would be much easier if you move the clock input to normal clock input pair.

Likely things to check if you can't move the clock.

1) Is the MGT that is associated with the REFCLK powered on your board?

2) Is the MGT REFCLKPWRDNB signal tied high?

3) Did you AC couple the REFCLK inptus for the correct signal levels?

Message Edited by mcgett on 03-20-2009 10:08 AM

[awdelp]

1)One of the MGT signals appears to have power the other doesnt.  

2)quick question :

where would i find REFCLKPWRDNB

3)Can you be a little bit clearer on this question.

By the way I'm really new to all programming aspects so forgive me for being ignorant.

Message Edited by awdelp on 03-20-2009 01:29 PM

[mcgett]

>1)One of the MGT signals appears to have power the other doesnt.  

I'm not sure what you mean by this

>2)quick question :where would i find REFCLKPWRDNB

 This is an input on the GTP_DUAL block.

>3)Can you be a little bit clearer on this question.

The reference clock inputs must be AC coupled, have a capacitor in series, to achieve the correct voltage levels. This is covered in the REFCLK guideline section of the Virtex-5 GTP User Guide.

[awdelp]

1) I tested to see if current was going through the pair of MGT clock signals and one of them had a voltage, while the other didn't.

2) I did find this, it says its tied_to_vcc_i   Do I need to change anything on it.

3)This has been checked by another person and I and is done correctly.

[awdelp · Accepted solution]

So, I believe I figured out the problem, and since no one seemed to have the answers I was looking for including webcase  I will respond to my own question.

The issue I was having was with a symbol IBUFDS.  By looking through the example verilog files generated from the core generator I figured out a way around it.

The lines you will need to add to your verilog file will be :

    TILE0_REFCLK_PAD_N_IN,
    TILE0_REFCLK_PAD_P_IN,               /// in your module port list area

    input           TILE0_REFCLK_PAD_N_IN;
    input           TILE0_REFCLK_PAD_P_IN;                   //////in your port decleration area

    wire            TILE0_REFCLK_I;                  ///wire decleration area

IBUFDS TILE0_REFCLK_IBUFDS_I
    (
        .O                              (TILE0_REFCLK_I),
        .I                              (TILE0_REFCLK_PAD_P_IN),
        .IB                             (TILE0_REFCLK_PAD_N_IN)
    );                                                                                                 /////main body of code

 .CLKIN_IN                       (TILE0_REFCLK_I),               /////  this will most likely say something similar to(CLK_IN) but you will want to switch it.  this is under "shared ports tile and PLL"

In your .UFC file make sure you have

NET "TILE0_REFCLK_PAD_N_IN"  LOC=AL4;                              /////where AL4, and AL5 are your respective positive and negative differential clk pins.

NET "TILE0_REFCLK_PAD_P_IN"  LOC=AL5;

Hope this helps anyone

[eamoody]

What do you mean by "it isn't an easy or clean solution"? 

I am working on a design using a  XC5VFX100T-2FF1136I.  Four transceivers, and two GTX tiles are used (112 and 114).  The line rate is 3.125 Gb/s and the input clock is 156.25 MHz.  The pwb design is incredibly tight, with almost no spare area.  We need to use the REFCLKOUT to clock the rest of the FPGA fabric, to avoid adding another oscillator or external clock buffer.

Is there a problem with this approach?  Thanks.