07-13-2010 05:42 AM
I am working on ML507 board. I intend to use Tri-mode Ethernet MAC Wrapper v1.6 IP core without processor(MIcroblaze or Powerpc )to establish connection from/to PC. I am a newer for Ethernet and my design is:
1. Creat Tri-mode Ethernet MAC Wrapper v1.6 IP core with CORE Generator
2. revise Verilog code, add RESET signal to Marvell chip
UCF: NET "Phy_rst_n" LOC = J14;
3. Download BIt file to FPGA, connect to PC
But LED for Marvell chip pins Led_Link10/100/1000 is not light?
Can anyone give me some suggestIon?
07-27-2010 11:30 AM
XAPP957 provides a working demo of GMII on the ML507 board. I'd recommend running this to make sure your board is setup correctly:
If you would like to just use the example design and target the ML507 I'd recommend:
1) using the ucf from XAPP957
2) using DCM to generate a 125Mhz clock (you could copy over the one from the xapp)
3) the phy reset that is connected to an FPGA output must be driven with an active low reset (the inverse of the reset to the TEMAC)
09-16-2010 12:02 AM
You can take a look at the following link which explains standalone example design for MAC wrapper
You have to make following modifications to make it work on ML507
Make the modification as described below:
1. Add PHY_RESET as an input port in the top level.
2. Add following in the UCF file. AK7 is just a push button. J14 is the reset line going to the PHY.
NET "RESET" LOC = "AK7";
NET "PHY_RESET" LOC = "J14";
3. PHY reset is active low. Add following:
PHY_RESET <= not reset_i;
4. Add following:
--instead of top level input signals
signal CLIENTEMAC0TXIFGDELAY_int : std_logic_vector(7 downto 0) := (others => '0');
signal CLIENTEMAC0PAUSEREQ_int : std_logic := '0';
signal CLIENTEMAC0PAUSEVAL_int : std_logic_vector (15 downto 0) := "0000000000000000";
signal PHYAD_0_int : std_logic_vector (4 downto 0) := "00111";
The phy address for phy0 is 7.
5. Comment out all of the following from the top level and put 'open' in the corresponding output ports of the module instantiation.
-- Client Receiver Interface - EMAC0
-- EMAC0CLIENTRXDVLD : out std_logic;
-- EMAC0CLIENTRXFRAMEDROP : out std_logic;
-- EMAC0CLIENTRXSTATS : out std_logic_vector(6 downto 0);
-- EMAC0CLIENTRXSTATSVLD : out std_logic;
-- EMAC0CLIENTRXSTATSBYTEVLD : out std_logic;
-- Client Transmitter Interface - EMAC0
-- CLIENTEMAC0TXIFGDELAY : in std_logic_vector(7 downto 0);
-- EMAC0CLIENTTXSTATS : out std_logic;
-- EMAC0CLIENTTXSTATSVLD : out std_logic;
-- EMAC0CLIENTTXSTATSBYTEVLD : out std_logic;
-- MAC Control Interface - EMAC0
-- CLIENTEMAC0PAUSEREQ : in std_logic;
-- CLIENTEMAC0PAUSEVAL : in std_logic_vector(15 downto 0);
-- EMAC-MGT link status
-- EMAC0CLIENTSYNCACQSTATUS : out std_logic;
-- EMAC0 Interrupt
-- EMAC0ANINTERRUPT : out std_logic;
6. In v5_emac_v1_5.vhd, change following:
constant EMAC0_PHYINITAUTONEG_ENABLE : boolean := TRUE; -- FALSE by default
8. Modify following in the UCF file:
INST "MGTCLK_N" LOC = "P3";
INST "MGTCLK_P" LOC = "P4";
9. Make sure the board is configured for SGMII.
03-03-2011 10:19 AM
I dont know enoght english to say to you how happy im right now, thanks a lot !!!!
By the way, how did you figure that out??? You used only the user guide?
03-04-2012 01:07 AM
I modify my FPGA TEMAC code according to your description, but my Ethernet LED is all not lighted (ML507 board).
Ethernet interface is SGMII and Jumpers J22/J23 is 2-3.
can you give me some suggestion?
And I don't know what MAC address of EMAC Core ? aa-bb-cc-dd-ee-ff?
why ML505_sgmii_design_creation data_sheet tell the address which is
arp -s 220.127.116.11 00-0a-35-01-8e-3b
i can't understand it!
can you tell me how to map IP address and EMAC address of TEMAC project and PC?
04-19-2012 01:50 AM
hi ,I have a design which may be similar as yours ,I am a novice in ISE , I plan to use the TEMAC core in my design , so for the first step ,I want to familier to it . I want to use the design example which was provided by the CORE GENERATION , I modified it as kotireddy.xilinx discribed , and downloaded the .bit file to the FPGA, my board is ML507 and the virson of my ISE is 10.3 , I did as the http://www.xilinx.com/products/boards/ml505/docs/m
04-24-2012 10:04 PM
thanks for your suggestion ,I read the PDF your provide and do some debugger , I give the details of the result on this thread
could you help me ...I have worked on it for some time , without any progressing ...