Connectivity

[doronkdoron]

Hi,

I am working on an optical communication system.

I am using virtex 4 fx60, ISE 11.1,  and I generated a 2 lanes aurora core v 3.1, each lane works on 1.26 Gb/s (using 125 MHz MGT clock), data width is 64 bits.

The "xilinx aurora example" works fine on chip (data transfers fine on sfp fibers out from MGTs), but when I try to transfer my frames (using frame generator that I connected instead of xilinx frame generator) every data word reaches to the RX side with error. The bits switch places in each word.

I have no Idea why this happens, I enter a data to TX side, and it reaches with errors on RX side. I tryed to generate the core from begginning but it didn't change the errors. 

It's important to say that I have used before on this chip 1 lane aurora, 32 bits, 2.488 Gb/s successfuly with othe MGTs.

I would appreciate help, We stuck a lot of time on this project because of this problem.

Doron.

[kka]

Can you provide few words that you are transmitting [TX side] and corresponding received data [RX side] for analysis?

[doronkdoron]

Yes, I hope this would help. most of the errors comes in this way, for example:

TX side : X"0123456789abcdef"

RX side : X"89ab45670123cdef"

example two:

TX side : X"0000000000000001"

RX side : X"0000000000000001" can't see the error, beacuse the 2 lower bytes always reach to the RX side in the same order they were sent  (see first example).

I have another relevant information: beacuse of our board design, I use 125 MHz MGT clock instead of 126 MHz clock that the core generator asked me to. 

Note that  the core generator can generate the core with minimal 1.26 Gb/s line rate ( which will ask 126 MHz clock)

(I will edit the first massage).

looking forward for your help.

[kka]

This is due to issue with GT REFCLK that is been provided for Virtex-4 FX Aurora 8B10B core.

If the core is generated with 126MHz, then 126MHz should be feed into the core.

Otherwise it will result in soft errors at RX side.

You can confirm this by looking at soft_error signal in top.

As of now, Virtex-4 FX Aurora 8B10B  core doesn't allow to generate the core for 1.25Gbps line rate.

Alternaively, you can generate the Wizard core  with same settings (line rate/REFCLK) from "Virtex-4 FX FPGA RocketIO Multi-Gigabit Transceiver Wizard" and change the attributes setting in the Virtex-4 FX Aurora 8B10B  core's tranceiver wrapper.

Hope this helps

[doronkdoron]

Thank you for your reply.

I just looked on the soft error bit and hard error bit also, they are constantly on 0 (no soft or hard error).

If I don't get soft errors, do you still think that the problem is the clock? plus, other costumer of you that I know, have the same fpga as I, and 125 MHz clock and the aurora core is working fine (he generated it same as I did). He uses aurora version 3.1, but a little older REV.

Getting 126 MHz clock is a trouble for me, it will take some time that I don't sure if I have. After I supplied you this information, are you still think switching the clock will solve the problem? maybe switching to anothe version will help?

Working on 2.5 Gb/s can be a problem for us beacuse I connect to another aurora 2.52 Gb/s, this means that the other person I'm working with will have to change his design too. I will do it if this is the last option.

looking forward for reply.

[kka]

Do you have acess to Virtex-4 transceiver ports?

Can you look at status of these signals which comes out of Virtex-4 MGT : RXDISPERR and RXNOTINTABLE

By looking at the received data, single bit change is observed.

Mostly it is due to soft errors.

Can you give me the following details:

1. Aurora core version that you are using?

2. Line rate

3. Reference clock frequency

I sugest to use latest Aurora core (Virtex-4 FX Aurora 8B10B v3.1).

The customer we have dealt was using old Aurora core had data integrity issues.

[doronkdoron]

Please try to be a little more clear. Why should I look at these bits, if the soft errors bits is constant on 0?

and in which module are these bits located?

The details you requested are written on first massage, again:

1. aurora 8b/10b for virtex 4 v3.1 REV 1.1.2.8

2. 2 lanes of 1.26 Gbit/s each = 2.52 Gbit/s (MGTs 112B, 113B)

3. 125 MHz mgt reference clock (ref2 right)

[kka]

Let us stop debugging in soft error direction. It may not be an issue.

It looks like your frame generator/checker might have issues with little/big endian conversion.

Can you look your code and make sure you have taken care of the byte ordering?

Can you confirm that with your 64-bit frame generator, core is working without data integrity failure in functional simulation?

(just to make sure)

[doronkdoron]

First, I found the bits you have sayed that I should be looking and they are constantly on 0.

I have tried before to run simulation of my design with my frame generator and it was working perfectly.

I have looked at my frame generator code, but it is a really simple one. It has a 8 byte register (signal) and it connects to TX_DATA port, the entity of my frame generator is same as xilinx's one. I can upload tomorrow my frame gen code, but I think it's not the issue...

[doronkdoron]

I can't see why my frame generator is the problem, because I see (using chipscope) that the TX_D data reaches to the TX_D side of the aurora correctly. any other ideas?

Is the fact that I don't have soft errors, terminates the odds that the MGT 125 MHz clock can be the problem?