05-16-2012 10:48 AM
I am trying to implement a decimated sine wave using a DDS in sysgen for a Virtex6. I am clocking the FPGA at 1/4 rate of the external DAC clock. (ie. FPGA=250MHz, DAC=1GHz). So for each FGPA clock (t) my 4 decimated sine wave outputs (n) need to be: t(0)=[n, n+1, n+2, n+3]; t(1)=[n+4, n+5, n+6, n+7]; etc.
Does anyone know of a clever technique for using a DDS to create a 1/4 rate decimated sine wave?
Solved! Go to Solution.
05-16-2012 01:59 PM
This has recently been discussed in a german forum. Somebody wanted to create a 2GB DDS without the given chips, or instead needed a digital output.
It was somewhere here, but I could not find it at the moment.
Well in fact you need 4 parallel DDS units operating at their full speed. If you are also smoothing and filtering the waves, this will also have to be done in parallel then.
At that point of time I too searched for something like that but did fail.
I really regret too, that the known chips of AD like 9912 do not have a digital output, because then you might get this function with 2GHz speed for some $ only.