05-16-2012 03:20 PM
I have recently been working on a real time digital audio equalizer implementet on an FPGA, using the Atlys board from Digilent, which has a Spartan 6 FPGA and an LM4550 AC97 audio codec. The filtering module has been implemented using System Generator.
At the current time, the system is working this way:
Audio is sampled using the AC97 controller module from the Digilent demo, and is read in a Microblaze processor. The samples are then sent to the filter module using shared memory blocks (FIFOs). The volume of the filter bands are determined by multiplying the samples with values sent from Microblaze to some shared registers in SG. Then Microblaze reads the filtered samples and sends them back to the AC97 controller, and to the DAC's. This is working fine at the moment.
However, I would rather like the audio to go directly to the filter module, insted of first going through Microblaze.
For this I have to make my own controller for the AC97. The AC97 data frames are 256 bits serial data. The start of each frame is determined by a sync pulse.
I need a way to convert the 256 bit serial data to parallell data, and i have to use the sync pulse to determine the start of the 256 bit frame. At first I thought of the 'serial to parallell' block, but it doesn't seem to have an inport for determining the start of the frame?
So: 256 bit serial data ---> 256 bit parallell data.
Does anyone know a way of solving this?
Best regards, Peter.
Solved! Go to Solution.
05-17-2012 02:32 AM
05-17-2012 05:56 PM
Thanks for the reply.
okay, but do you mean I can look at the controller as a block diagram somehow? If so, how can I do this? I can only find VHDL/verilog files for the controller, and I haven't really learned HDL yet.
05-17-2012 06:11 PM
Don't worry, there are no silly questions!
There are a few block diagram-esque representations you might come across when working with Xilinx products - schematic capture, System Generator, and EDK's peripheral-connecty-thingy spring to mind, but it's good to get your hands dirty with HDL.