DSP Tools

[droid77]

Hello,

I am trying to implement a second order, butterworth, bandstop filter with a notch frequency of 60 Hz, and with a sampling rate of 100KHz.  I have begun to do this using the "fdatool", using a Direct-Form I Structure and also using the "Convert to single section" option in the fdatool's Edit menu.  I then exported my subsystem to Simulink environment and also built a functionally equivalent subsystem using the System Generator blocks.  I then simulated them side-by-side to observe performance differences and the subsystem implemented using the fdatool works as designed but the SysGen subsystem is not.  I think it might be a quantization error and I have tried modifying the precision of blocks with no success.

I have attached a screenshot of the fdatool settings and the model file in question

Any advice in helping me troubleshoot this problem would be greatly appreciated.

Thanks for your time.

[vlavruhin]

Hello.

1. What is the purpose of 'Delay6' block in sysgen's implementation? Remove it ot set zero latency. Otherwise, output register will latch wrong sample.

2. When you are dealing with the fixed-point numbers, you should pay an attention to bitwidths and binary point position. Your input signal has amplitude 50. Then 'Gateway In' block samples it with fixed-point representation 'Fix18_0'. 'Fix18_0' means that samples are in range [-2^17; 2^17-1] = [-131072; 131071]. I.e., your input signal has amplitude 20*log10(50 / 131072) = -68.37 dB (of full 18 bit scale). I guess, you would like to use higher amplitude. So check carefully all your fixed-point formats, especially after the multiplications.

3. Add 'Gateway Out' blocks to suppress warning message.

4. FDAtool allows you to quantize designed filter with custom intermediate fixed-point formats. So you can check whether your filter is stable with current quantization.

5. If you are using System Generator 13.4, then you can set floating-point arithmetic in properties of the multipliers and input gateways.