Hi,
I've been working with Simulink and System Generator in MATLAB R2006a and Xilinx EDK version 8.102i.
In EDK I have set up a Microblaze processor. In Simulink I have created a 'From FIFO' with depth 32 which takes data from the Simulink design and connects to the EDK processor via the memory map set up in the 'EDK processor' block in the design.
The design in Simulink successfully generates as a PCore for use with EDK. The PCore has then been successfully attached to the Microblaze processor in EDK using a FastSimplex link. I have then written a simple program for the Microblaze processor which reads the status and data registers of the From FIFO, using the driver commands provided: e.g.
status = test_sys_sm_0_Read(TEST_SYS_SM_0_From_FIFO, TEST_SYS_SM_0_From_FIFO_Data, data);
This system builds and downloads into my hardware, a Virtex II Pro on a Digilent Virtex II Pro Development System board perfectly.
When I run this system and monitor it using output from the serial port I can tell that:
- Data values from the Simulink logic are being entered into the FIFO and it is filling up
- Read commands carried out on the FIFO by the Microblaze processor are resulting in the FIFO occupancy value being reduced
- Read commands are failing to return valid data, the return value of the read command is '-1' instead of '0' for a successful read.
Is this something to do with a know issue? Are there any updates which fix this?
Thanks in advance,
Rich
