DSP Tools

[wgartner]

Dear Colleagues!

I created a design in System Generator and put it into the ISE Project Navigator. In ISE I have only the System Generator Files and a Test bench (no additional Entiteis). When I try to simulate the design I get the following messages.

Starting static elaboration
ERROR:HDLCompiler:1030 - "N:/O.40d/rtf/vhdl/src/XilinxCoreLib/dist_mem_gen_v6_1.vhd" Line 210: Cannot open file 'meminitfile'.
ERROR:Simulator:777 - Static elaboration of top level VHDL design unit top_top_sch_tb in library work failed

(I do not have an N:\ Disk. )

Please HELP!!!

Greetings from Austria

Wolfgang

[dima2882]

I have a similar issue when trying to simulate a core I made using System Generator, using 13.4 and Isim:

Starting static elaboration
ERROR:HDLCompiler:1030 - "N:/P.7xd/rtf/vhdl/src/XilinxCoreLib/c_shift_ram_v11_0_legacy.vhd" Line 193: Cannot open file 'initfile'.
ERROR:Simulator:777 - Static elaboration of top level VHDL design unit wgng_axi_mcw in library work failed

Process "Simulate Behavioral Model" failed

I, too, do not have an N: drive. I see the c_shift_ram_v11_0_legacy.vhd file in ISE, but something weird is causing it to bug out... Has anyone seen something like this before?

[ambrosef]

This is likely due to relative paths to the mem file in the produced Sysgen HDL code. Please modify the HDL provided by System Generator to contain the full path to the mem init file instead of the relative path.