DSP Tools

[robotiker007]

Hello, 

I'm trying to migrate my design, from ISE 9.1 to ISE 13.4 and a lot of things have change.

I have a Digital Down Converter, and I implement it whit DAFIR, now in the new System Generator, I have to choose FIR COMPILER 5, with the Distributed Aritmethic ta checked. If I try to generate a first decimator by a factor of 2 with the Systolic, or acumulative mult I have no problems, but if I try to generate a decimator with Distributed arithmetic I have no decimation at the output of the filter. I can´t use Systolic, because I have not enought DSP 48 in my spartan 3ADSP, I attach an image of an example of what is happening. Althougt I do a decimation, at the output of the filter I have the same freq.

Any help will be very gratefull.

[bwiec]

In the SysGen block, in the General tab, can you select 'Normalized Sample Periods' for the block icon display and see what happens?

[ywu]

Take a look at the thread below:

http://forums.xilinx.com/t5/DSP-Tools/filter-compiler-5-0-in-Distributed-Arithmetic-mode-problem/m-p...

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robotiker007 wrote:

Hello, 

I'm trying to migrate my design, from ISE 9.1 to ISE 13.4 and a lot of things have change.

I have a Digital Down Converter, and I implement it whit DAFIR, now in the new System Generator, I have to choose FIR COMPILER 5, with the Distributed Aritmethic ta checked. If I try to generate a first decimator by a factor of 2 with the Systolic, or acumulative mult I have no problems, but if I try to generate a decimator with Distributed arithmetic I have no decimation at the output of the filter. I can´t use Systolic, because I have not enought DSP 48 in my spartan 3ADSP, I attach an image of an example of what is happening. Althougt I do a decimation, at the output of the filter I have the same freq.

Any help will be very gratefull.

---

[vlavruhin]

Hello.

The output is decimated. Look at RDY port of the filter. The problem is that different configurations of FIR compiler produce different implementations of decimated signal: in one case output is decimated (in sense of Simulink sample time) and RDY value is always true, in other case output signal of the filter doesn't seem to be decimated, but if you check RDY port, you'll see the pulses at decimated sample time.

Look at a thread suggested by Jim for more information.

Hope it will help you. If not, feel free to ask questions.

[robotiker007]

Thank you  very much for the answers.

The results of the decimation as you can see in the image attached, are correct, I have to fight to obtain good results in the upsampling. I only can achive an upsampling x2, when I try to upsample for another factor of 2 I obtain an extrange result as you can see in the last scope channel, wher the signal is not synchronised,.

Any Idea?

[robotiker007]

The design is very simple 3 downsample chain an at least 2 upsample not working at all.

[vlavruhin]

Hmm...

Why you are not using link "RDY -> ND" for all filters?

[robotiker007]

The problem is that if in the first upsampler I use the rdy output of the last downsampler, I obtain this scope. 

The upsampler doesn`t work fine. You can check that the first upsampler is not working.

I left the new scope and the new design changing the rdy connection.

The first upsampler only works if I introduce in its nd a boolean '1' signal whit 4/fs freq.

If you want I can attach the design?

Thank you very much for your help.

[robotiker007]

design 

[robotiker007]

I attach the design, if anyone have couriosity.

The fs is 121.76 Mhz.

Thanks