DSP Tools

[tdeyle]

I'm trying to create a very simple low-pass filter using FIR Compiler.  The design synthesizes successfully until the very last step ("Generating Verilog structural model."), at which point it fails with the following error:

ERROR:coreutil:1010 - Command '/opt/Xilinx/13.4/ISE_DS/ISE/bin/lin/netgen -intstyle ise -w -sim -ofmt verilog "./tmp/_cg/sample.ngc" "./tmp/_cg/sample.v" ' failed, returning a non-zero exit code '2':

/opt/Xilinx/13.4/ISE_DS/ISE/bin/lin/netgen: application received signal 6.

ERROR:sim - Error found during generation.

This final synthesis step seems to be related to the "preferred simulation model" of the CoreGenerator project, as it occurs for both the "behavioral" or "structural" settings (but not when set to "None").  My ISE project (seems to) requires the simulation model, since it complains about its absence and forces a core regeneration to sythesize the top-level design (which then fails due to this error again).

This error is currently blocking my progress... so any help is _GREATLY_ appreciated.  (Oh, and I've already attempted the suggestions in AR#43865 as suggested by the other coreutil:1010 error post.)

Setup Details:

ISE 13.4 on Ubuntu 11.10 32-bit.

Core Generator 13.4

Part: xc4vfx20-10ff672

Design Entry: Verilog (Behavioral Simulation)

 Full Core generation info log:

Welcome to Xilinx CORE Generator.

Help system initialized.

The IP Catalog has been reloaded.

Opening project file /home/travis/dragonfly/ise/blinkenlights/ipcore_dir/coregen.cgp.

Closed project file.

Opening project file /home/travis/dragonfly/ise/blinkenlights/ipcore_dir/coregen3.cgp.

Closed project file.

Wrote CGP file for project 'coregen4'.

Customize and Generate

INFO:sim:172 - Generating IP...

Applying current project options...

Finished applying current project options.

Customizing IP...

Release 13.4 - Xilinx CORE Generator IP GUI Launcher O.87xd (lin)

Copyright (c) 1995-2011 Xilinx, Inc. All rights reserved.

Finished Customizing.

Generating IP...

WARNING:sim:472 - The chosen IP does not support a Verilog behavioral model, generating a Verilog structural model instead.

XST: HDL Compilation

XST: Design Hierarchy Analysis

XST: HDL Analysis

XST: HDL Synthesis

XST: Advanced HDL Synthesis

XST: Low Level Synthesis

Generating Implementation files.

Generating padded file...

Generating the Verilog wrapper.

Generating NGC file.

Generating padded NGC file.

Generating Verilog structural model.

ERROR:coreutil:1010 - Command '/opt/Xilinx/13.4/ISE_DS/ISE/bin/lin/netgen -intstyle ise -w -sim -ofmt verilog "./tmp/_cg/sample.ngc" "./tmp/_cg/sample.v" ' failed, returning a non-zero exit code '2':

/opt/Xilinx/13.4/ISE_DS/ISE/bin/lin/netgen: application received signal 6.

ERROR:sim - Error found during generation.

Closed project file.

Opening project file /home/travis/dragonfly/ise/blinkenlights/ipcore_dir/coregen4.cgp.

FIR Compiler Core settings:

[Default values, except...]

Coefficient Vector:-0.014823, -0.062604, -0.020915, -0.02299, -0.00054732, 0.028623, 0.065371, 0.10352, 0.13694, 0.15979, 0.16794, 0.15979, 0.13694, 0.10352, 0.065371, 0.028623, -0.00054732, -0.02299, -0.020915, -0.062604, -0.014823

Input Samp. Freq: 125

Clock Freq: 125

Also... in an odd and somewhat related error... after this failure, the Core Generator project indicates that FIR Compiler is not supported for my device until I switch to a new device, then back.  That's odd.

[tdeyle]

This just got even more weird... running CoreGenerator with Verilog fails (FIR Compiler all default settings), but VHDL succeeds!?  Why would this be the case?!

[bwiec]

First of all, Ubuntu is not a supported OS. Which means we don't test it so some issues are possible.

When you generate a core and have selected to produce a structrual simulation model, XST is first run on the core, then the resulting NGC netlist is sent into a utility called netgen which generates the structural simulation model. To diverge a bit, if a particular core doesn't have a behavioral simulation model and you have selected 'behavioral' option on coregen, it will give you a warning and let you know that it's defaulting to generating a structural simulation model. A number of our DSP cores in particular have behavioral VHDL models, but no behavioral verilog models. Thus the difference between VHDL and verilog generation.

What you can try is selecting 'none' for the simulation model in coregen. Then you can take the resulting netlist and run netgen manually to try and generate a simulation model. You could try different switches to see if you can get around it. See the Command Line Tools User's Guide for more information.

Alternatively, you could use the VHDL models if you have a mixed language simulator/license.