07-04-2012 06:37 AM
When I am building an FIR system which is to be running at a sampling frequency of 96KSPS but my FPGA has a 100MHz clock, I would need to program the Gateway In (obviously, I am working in xilins system generator/matlab simulink environment) to the Sampling frequency I want the FIR to be working with. That is to say that even though the FPGA is running is normal clock, between the Gateway In-Gateway Out the system is running at Sampling Frequency rate I want. Do you have an example that shows this affect.
07-04-2012 10:43 AM
I would recommend looking at the Clocking and Timing section of the Sysgen User's guide. It explains much of this in great detail with some good examples.