I have a setup where Xilinx ML506-board controls motor drive, and it's very important to know what happens if the ethernet connection fails.
The control itself is implemented to run independently in the FPGA-board (with VHDL-black boxes and System Generator Blocks), but I use co-simulation to exchange monitoring data and basic higher-level user control (power on/off, etc....) with shared memory blocks (to user GUI made with Matlab GUIDE).
Now, for example, if I stop the simulation all shared memory blocks which have been set to initialize to some value (for example boolean high state, where the control logic is active low for power on/off control) are set to zero which results in forbidden behavior (power and all other active low logic is driven to active state).
So, the question is, has the behavior of the HW Co-Sim been documented in the case of a lost ethernet connection and are there any possibilities to control the behavior? Would be nice if the free clock running control logic could keep running in the FPGA, and be able to reconnect to the FPGA-board without disturbing the control itself.
