07-02-2010 09:15 AM
when I try to generate a hardware co-simulation target (ML402 Ethernet P2P) from the example code in
I get the following error:
Checking model status
Checking simulation times
Performing compilation and generation
Compilation and generation completed in 875.1302 seconds
*** ERROR ***
An error was encountered while compiling the design for hardware co-simulation. Please refer to hwcosim_compile_error.log for details.
Checking the contents of hwcosim_compile_error.log does not reveal much:
Java exception occurred:
at com.xilinx.sysgen.netlister.m.a(Unknown Source)
at com.xilinx.sysgen.netlister.m.if(Unknown Source)
at com.xilinx.sysgen.netlister.m.do(Unknown Source)
I get this with both MATLAB 2009a and 2009b (ISE 12.1). Any help tracking down the source of this problem is much appreciated!
Solved! Go to Solution.
07-03-2010 12:32 PM
07-07-2010 02:58 AM
I've gone back to ISE 11.5 and narrowed down the problem to the following blocks: "Shared Memory" and "To/From FIFO". Interestingly, the "To/From Register" block works fine and does not lead to the error.
07-07-2010 03:23 AM
so you use "To/From Regiter" to replace "To/From FIFO", it fixes errors? If so, you can build a fresh design which only includes To/From FIFO to see whether it works.
07-07-2010 03:42 AM
even a fresh design with a "To/From FIFO block" comes back with the same errors. As an illustration, please look at the attached examples.
Example1: compiles fine!
Example2: same design, but the register is replaced by a FIFO -- errors as above.
07-18-2010 09:31 PM
This is due to an issue with generating Shared Memory or FIFO core in hardware co-sim flow, which requires write permission to the SysGen directories.
A workaround is to make the SysGen directories writable, e.g. on Linux,
chmod -R a+w <sysgen install directory>
This issue will be fixed in future releases of SysGen.