DSP Tools

[mafgani]

Hi,

when I try to generate a hardware co-simulation target (ML402 Ethernet P2P) from the example code in

Xilinx/12/ISE_DS/ISE/sysgen/examples/shared_memory/hardware_cosim/conv5x5_video/

I get the following error:

Begin generation
Checking model status
Checking simulation times
Performing compilation and generation
Compilation and generation completed in 875.1302 seconds

*** ERROR ***

An error was encountered while compiling the design for hardware co-simulation. Please refer to hwcosim_compile_error.log for details.

Checking the contents of hwcosim_compile_error.log does not reveal much:

Java exception occurred:
com.xilinx.sysgen.netlist.NetlistInternal:
    at com.xilinx.sysgen.netlist.PerlScripter.quickCall(Unknown Source)
    at com.xilinx.sysgen.netlist.PerlScripter.quickCall(Unknown Source)
    at com.xilinx.sysgen.netlister.m.a(Unknown Source)
    at com.xilinx.sysgen.netlister.m.if(Unknown Source)
    at com.xilinx.sysgen.netlister.m.do(Unknown Source)
    at com.xilinx.sysgen.netlister.HwcosimWrapperBuilder.a(Unknown Source)
    at com.xilinx.sysgen.netlister.HwcosimWrapperBuilder.buildHwcosimFiles(Unknown Source)

I get this with both MATLAB 2009a and 2009b (ISE 12.1). Any help tracking down the source of this problem is much appreciated!

[ticktack]

Normally ": java.lang.NullPointerException" is caused by the windows language settings

"

[mafgani]

Afraid not .. I'm running this on Centos 5.4 (RHEL 5.4 Clone). Other compilation targets such as "HDL Files" and "Bitstream Generation" work just fine. I get the error only with the Hardware co-sim targets.

[ticktack]

How did you run HWCosim? It occurs if you run it in command line. If you run HW-Cosim in GUI, it should be fine.

[mafgani]

I run it via the System Generator token (by clicking 'Generate') in my design. So, via the GUI.

[mafgani]

I've gone back to ISE 11.5 and narrowed down the problem to the following blocks: "Shared Memory" and "To/From FIFO".  Interestingly, the "To/From Register" block works fine and does not lead to the error.

Any ideas?

[ticktack]

so you use "To/From Regiter" to replace "To/From FIFO", it fixes errors? If so, you can build a fresh design which only includes To/From FIFO to see whether it works.

[mafgani]

Hi,

even a fresh design with a "To/From FIFO block" comes back with the same errors. As an illustration, please look at the attached examples.

Example1: compiles fine!

Example2: same design, but the register is replaced by a FIFO -- errors as above.

[benchan · Accepted solution]

This is due to an issue with generating Shared Memory or FIFO core in hardware co-sim flow, which requires write permission to the SysGen directories.

A workaround is to make the SysGen directories writable, e.g. on Linux,

chmod -R a+w <sysgen install directory>

This issue will be fixed in future releases of SysGen.

[mafgani]

That did it! Thanks benchan!