Sign In

Don't have a Xilinx account yet?

  • Choose to receive important news and product information
  • Gain access to special content
  • Personalize your web experience on Xilinx.com

Create Account

Username

Password

Forgot your password?
XClose Panel
Xilinx Home
Reply
Visitor
wangsf1112
Posts: 7
Registered: ‎12-26-2011
0

Hardware co-simulation , non-memory mapped ports

 

hi,

   there is a question about  non-memory mapped ports.

 

    I do a Hardware co-simulation compilation type with my hardware platform,and creat a A/D non-memory mapped ports. But when I generate code,and hardware simulation, I can't get the correct data from external signal.

 

So is there anyone help me with this problem?  thanks.

Xilinx Employee
vsrunga
Posts: 60
Registered: ‎07-11-2011
0

Re: Hardware co-simulation , non-memory mapped ports

Hi

 

I am expecting you are using Jtag based custom board Hardware Co Simulation,

"Not getting correct data " means ?

Are you comparing simulink simulation against HW CO SIM results , if so wthat is clocking type ?

It depends on single stepped or free running.

Free running results may not match as Hardware runs asynchronoulsy with software simulation.

 

Snapshots may be useful for better understanding.