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How do I operate the warning when I use the project produced by System generator .
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04-06-2012 09:16 PM
Hi:
I creat a model in System generator .After SG and creat a lot of file include a ISE project file.I load it in Xilinx ISE directly and synthesis.There has so much warnings and I donot know how to deal with them.Would anyone can help me, thanks very much!
**************************************************
WARNING:Xst:2211 - "radar_cw.v" line 422: Instanti
WARNING:Xst:37 - Detected unknown constraint/prope
WARNING:Xst:37 - Detected unknown constraint/prope
WARNING:Xst:37 - Detected unknown constraint/prope
WARNING:Xst:2211 - "radar.v" line 82760: Instantia
WARNING:Xst:2211 - "radar.v" line 82830: Instantia
WARNING:Xst:2211 - "radar.v" line 82934: Instantia
WARNING:Xst:2211 - "radar.v" line 82945: Instantia
WARNING:Xst:2173 - Found black boxes on which forw
WARNING:Xst:2174 - These might be cores which have
WARNING:Xst:616 - Invalid property "SYN_NOPRUNE 1"
WARNING:Xst:616 - Invalid property "SYN_BLACK_BOX
WARNING:Xst:616 - Invalid property "SYN_NOPRUNE 1"
WARNING:Xst:616 - Invalid property "SYN_BLACK_BOX
WARNING:Xst:616 - Invalid property "SYN_NOPRUNE 1"
WARNING:Xst:616 - Invalid property "SYN_BLACK_BOX
WARNING:Xst:616 - Invalid property "SYN_NOPRUNE 1"
WARNING:Xst:616 - Invalid property "SYN_BLACK_BOX
Re: How do I operate the warning when I use the project produced by System generator .
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04-17-2012 11:25 PM
Hi,
when you run the netlist or bitstream creation directly from sysgen and then take a look at the reports (e.g. *.syr) you probably see the same messages.
The code created by sysgen is mainly some structural HDL description which causes the XST tool to create many black boxes that are replaced later on by generated coregen IP blocks. That's the way it goes, and so the warnings can be ignored. The other warnings about missing properties probably as well. Sometimes such stuff remains to ensure compatibility between different tool and IP-core versions.
The tool triangle Matlab/Simulink - sysgen - ISE is very complex and has many fragile dependencies.
So don't be irritated by a high number of Warnings as long as there are no Errors.
Give your code a try in some simulation (behavioral, post-PAR or even better: HW-Cosim) and if it works there try it on the FPGA.
Have a nice synthesis
Eilert











