05-21-2012 12:05 PM
I want to implement a counter that I increment at the clock rate (12.5e-9 seconds) but I want to decrement the counter at different rate (1.0075e-5 seconds). How can I implement this since the the counter block specifically asks for a single rate?
Can you provide a simple model file to illustrate a possible solution?
Many thanks for your time.
Solved! Go to Solution.
05-22-2012 04:31 AM - edited 05-22-2012 04:32 AM
Consider that you would like to design a counter, that counts up at the frequency f1 and counts down at the frequency f2. Lets suppose that f1 = K * f2 (K - some integer number).
It's really easy to describe the behavour of such counter using your favourite HDL. It should be clocked by the frequency f1. At each rising edge of f1 the counter counts up. And at each K clock cycles of f1 the counter counts down. To detect these K cycles additional counter that counts down from K to 0 can be used.