DSP Tools

[kchalla]

Hi,

I have a problem in integrating different netist generated (using system generator in Simulink) files. I have two different models. I have added the concerned *.ngc and *.vhd files to the Xilinx Project for Spartan 6. When i m adding the second netlist files then i have lot of warnings like

->WARNING:ProjectMgmt - Duplicate Design Unit 'structural' found in library 'work'

->WARNING:ProjectMgmt - Duplicate Design Unit 'default_clock_driver' found in library 'work'

->WARNING:ProjectMgmt - Duplicate Design Unit 'behavior' found in library 'work'

->WARNING:ProjectMgmt - Duplicate Design Unit 'xlclockdriver' found in library 'work'

and so on.....

As we can see they are found in both the *.vhd files.

When i have added only one netlist files then everything working fine. Once i add the second netlist files then its not working.

Does anyone have idea how to integrate properly different netlist files to the project?

Thanks in advance.

Best Regards,

Kiran

[bwiec]

I think the section titled "Importing a System Generator Design into a Bigger System" in the SysGen user's guide will answer your questions. Particularly, have a look at the step-by-step example which states:

"When integrating two or more System Generator designs into a bigger design, you need to
rename HDL libraries to prevent name clashes and other undesired behaviors during
simulation. System Generator provides a utility that switches library names for all related
files in your System Generator design."

See the doc for more!

[kchalla]

Hi bwiec,

thanks for your reply. I have read the document and applied what they wrote in the document and still not succeded.

When i m adding the *.sgp files i can see one error like

Entity <design_cw> compiled.

Entity <design_cw> (Architecture <structural>) compiled.
vhdtdtfi:Declaration (Module design_cw) not found.
tdtfi(vhdl) completed with errors.

syntax: xlSwitchLibrary(<target_dir_pathname>, <from_lib_name>, <to_lib_name>)

xlSwitchLibrary('design_netlist','work','design_lib')

may be i m thinking its the problem with the path.

'desing_netlist' is the path where the hdl generated files.

Can you please tell me what about the path of 'work' and 'design_lib'?

Or am i having other problem other than path?

Thanks & Regards,

Kiran

[ilovephysics]

Right now, I have the EXACT SAME problem as kchalla described above. I would also appreciate any help!

In addition, even after following the steps in the system generator guide, I still get all the duplicate warnings. By clicking on the "libraries" tab in ISE, I can see that I still have only only library named "work". 

[kchalla]

Hi,

As i m having more cores there are lot duplicate design units. It seems they take extra resources also.

So i want to make sure that there are no duplicate design units and they share the common design units by creating like package file.

But I dont know how to make it? As we see there is lot of code and it ll be challenging to separate the common design units from different cores.

As i see "xlSwitchLibrary" command only renames the design units. It means still the same design units are there but with different names. So its of no point if i want to save hardware resources.

The above said is my thinking. I may be wrong. So i need help from profis n fpga geeks ...:)

thanks in advance.

Best Regards,

Kiran