JTAG : strange behavior

caccolillo · ‎09-09-2010

Hello there, I'm a student at the University of Naples , Federico Secondo , Italy , and unfortunately I'm in trouble with my thesis. Let me explain the matter.
I'm trying to do a hardware in the loop simulation in order to validate "a bit serial stochastic" implementation of an ICM pulsed neural network,but I'm having some problem.
Due to the massively parallel nature of this video elaboration system applied to biometric purposes , the speed of execution is of vital importance , in order to motivate and validate projectual decisions as early as possible.
My software toolchain is the following: Matlab 2008a , Xilinx design suite 11.1, System generator 11.1.
The hardware I'm using is the following : Digilent low cost Jtag programming cable (the cheap version for the parallel port I mean) , Digilent Nexys2 FPGA Board .
The software simulation of my model is fine ; so I'm sure it's ok.
Problems arise when I try the hardware in the loop simulation.
I've followed faithfully the procedure stated in the "System generator for dsp , use guide" to build up the Simulink model.
I've also generated the "Board Support Package" as indicated in "System Generator for DSP: Performing Hardware-in-the-Loop with the Spartan-3E Starter Kit" document.
When I try the hardware in the loop simulation , the model behaves in a totally different way than it does with the system generator SW simulink simulation , exhibiting an erratic behavior.
I give up , at this point all I can do is just scratch my head to figure out what's wrong.
I've used a black box to model the whole ICM neuron in stochastic arithmetic , the vhdl code is ok . I've extensively simulated it on Xilinx ISE Isim , both in post-route and behavioral ,comparing final results between Isim and simulink, so I'm absolutely sure that isn't a VHDL code problem.
On the HW co-simulation block I've specified "Parallel cable IV" as it was the nearest thing to the cable which I had handy.
It's cristal clear : there's a problem with the toolchain , but I can't figure out what's wrong.
Maybe a problem with the non Xilinx cable?
Please , help me to awake from this nightmare.
Best regards,
Marco Aiello
( caccolillo )

driesd · ‎11-28-2007

Dear Marco,

I think there are a couple of things going wrong.

The most important problem is that the Nexys2 board isn't the same as the "Spartan-3E starter kit".

The starter kit is this board: Spartan-3E starter kit

The hardware is similar (Spartan-3E 500) but not the same. For example the hardware co-sim needs to know on which pins the clocks come in.

Are you sure the Spartan-3E starter kit is in the list? I thought only the Spartan-3A DSP starter kit is supported by default.

There is normally a way to define a custom target: check this thread.

2nd problem is your cable: sysgen does not support the digilent low cost programming cable which is compatible to the "Parallel Cable III" not the "IV".

You either need to get another cable or a board that does hardware co-sim over ethernet or a board that has a built-in download cable (for example Spartan-3E starter kit, SP601, SP605, ML605, ...)

Lastly, I would recommend you to upgrade to the latest update of ISE11: ISE11.5.

Like a lot of software, there are frequent updates which solve a lot of problems.

Best regards,

Dries

driesd · ‎11-28-2007

update: to add support for your Nexys2 board in sysgen, you should read chapter 3: Supporting New Platforms through JTAG Hardware Co-Simulation of the System generator userguide: link

Best regards,

Dries

caccolillo · ‎09-09-2010

Thank you for your swift and detailed response.
I appreciate it very much.
I've mentioned the "System Generator for DSP: Performing Hardware-in-the-Loop with the Spartan-3E Starter Kit" only for reference , it states in a very clear way the right procedure to follow in order to define a custom target (the paragraph "Generate Board Support Package Step 1" at page 1-2 I mean).
I've checked the digilent's UCF file for the Nexys 2 board , I'm aware that is a different hardware , so , in my opinion , I'm reasonably sure that isn't a matter of wrong board support package generation.
Regarding the software upgrade , it would be a very great idea , but unfortunately here at Naples we've got a shoestring budget , so it won't be possible.
It's a great mess because your software toolsuite is very great!
What a wonderful software.
Compliments.
Best regards,
Marco Aiello
( caccolillo )

driesd · ‎11-28-2007

Hi Marco,

It's not unlikely that a minor update (from ISE11.1 to ISE11.5) still is possible.

If you're out-of-warranty, indeed a major update (to ISE12) is likely not allowed.

What is the out-of-warranty date of your license?

Best regards,

Dries

driesd · ‎11-28-2007

caccolillo wrote:

Thank you for your swift and detailed response.
I appreciate it very much.

I can always KUDO posts if you like them.

caccolillo wrote:

I've checked the digilent's UCF file for the Nexys 2 board , I'm aware that is a different hardware , so , in my opinion , I'm reasonably sure that isn't a matter of wrong board support package generation.

OK, good. Then it's likely the download cable that is causing problems.

Can you use another board or lend a download cable?

Best regards,

Dries

caccolillo · ‎09-09-2010

Oh I see.
I had some suspect about the cable , but I wasn't sure at all.
Unfortunately the only board I can use is the Nexyx 2 .
Once more question.
I was just thinking to use the Platform cable USB , but the problem is that it has a 14 pin JTAG interface , while the Nexys 2 has only 6 .
Can I wire wrap on a perfboard an adapter in order to route the right signals in the right place realizing an hand made adapter , or is required some sort of signal buffering or level translator?
I thank you once again for your invaluable helping hand.
Best regard,
Marco Aiello

Best regards,

Marco Aiello