03-15-2012 07:20 AM
Im trying to implemt an lp-filter as a IP modul in XPS. But him having som truble figure out what kind of samplerate my sysgen is running at.
I know that the from register is geting data at 24kHz, but what kind of sample rate is the 2n-tap filter running at? The clock pin in system generator is connect to my gclk(100MHz).
03-15-2012 09:06 AM - edited 03-15-2012 09:07 AM
It runs at whatever your sysgen clock rate is. In your case, 100MHz.
If you right click the MAC FIR block and select 'Look Under Mask' you will see the filter architecture.
03-16-2012 03:26 AM
First of all, it's bad idea to feed input signal through Register.
Registers are good for parameters setting, but not as signal input/output ports.
As Bwiec said, your system generator design (and FIR filter) will be running at sysgen_clk = 100 MHz.
But Register is connected to Microblaze with aid of AXI / PLB bus (with different clock).
So there is no guarantee that every new sample of input signal will be processed by filter only once.
In your case sysgen_clk = 100 MHz, fs_input (writing 'From Register') = 24 kHz. If we divide one by other, we'll get K = sysgen_clk / fs_input = 4166,67. It means that every input sample will be processed by filter 4166 times.
I assume that you are reading 'To Register' (output samples) with sampling rate = fs_input = 24 kHz. So if filter order is less than 4166, then nothing will be filtered at all.
03-17-2012 02:24 PM
The best way to input signal in the System Generator model is 'Gateway In' block.
If you need to feed data directly from Microblaze (not from external port), then you should deal with synchronization between peripheral bus (AXI) and System Generator model. I.e, your System Generator model should process every input sample value only once. And your Microblaze core should write data to System Generator peripheral core only when this core is ready to process this data.
To do that you need to use some kind of additional FIFO buffer and Enable signals.
03-19-2012 10:46 AM
For interfacing to processor systems make use of the shared memories and as suggested make use of the FIFO shared memories as well. Also note that you have a export sysgen design as a Pcore option as well
03-21-2012 03:02 AM
So i shood use FIFO blocks insted of the from/to register block, is there an example somewhere that i can look at for some more info?
I tryed to use gateways, but how do i acsess them from microblaze?
03-21-2012 04:02 AM
Yes, you can't directly access to gateway ports from Microblaze. Gateway ports are the best way to input/output external signals. Or you can write intermediate "glue" logic in HDL for interfacing gateway ports to Microblaze bus.
But it's easier to use FIFO blocks. The main problem here is to control data flow between Microblaze and signal processing core. It can be done with aid of Read/Write/Chip Enable signals and Empty/Full FIFO signals. Also you should use 'FIR Compiler' block as filter IP where you can turn on ND and RDY control signals (which let you control data flow).
Please read System Generator User Guide for more information (second chapter 'Hardware/Software Co-Design)':
You can find there a sample model 'AXI Embedded DSP Application with FIR Compiler and Shared Memory blocks' at page 210.