Sign In

Don't have a Xilinx account yet?

  • Choose to receive important news and product information
  • Gain access to special content
  • Personalize your web experience on Xilinx.com

Create Account

Username

Password

Forgot your password?
XClose Panel
Xilinx Home
Reply
Visitor
rkr_eng
Posts: 3
Registered: ‎04-02-2012
0

Passing an image directly into the Shared (locked) Memory block

Hi,

I would like to pass an image straight to the shared (locked) memory via the 'shared memory write', read the processed image back from shared (locked) memory via 'shared memory read' and display the processed image on the host PC. I am able to compile, run and co-simulate with hardware the hardware_cosim real time video processing demo conv5x5_video as described in system generator user guide on page 272. I have installed Sysgen 13.3 with Matlab 2011a on Windows 7 PC.

 

I am trying to use the conv5x5_video_ex block as it is and would like to use only an image to be sent to the block for processing. Video is made from images and the block process them an image at a time so I kept this block as it is, without any modification.

 

I I have tried modifying the conv5x5_video_testbench.mdl. I removed the reference to the default preload function and wrote a new matlab function to create image array. I tried passing an image of 128x128 size converted to a 16384 byte array in matlab and then feeding it to the 'from workspace' block. I changed the property of the 'from workspace' block from 'cyclic repetition' to 'setting to zero'. I also limited the simulation time according to the image size instead of being infinite. I connected the testbench to the generated conv5x5_video_ex block. I also set the priority correctly.

 

The errors that I got

An internal error occurred in the Xilinx Blockset Library.

or

the System Generator hierarchy error.

 

Xilinx Employee
chrisar
Posts: 383
Registered: ‎08-01-2007
0

Re: Passing an image directly into the Shared (locked) Memory block

Its hard to say what's going wrong.  This is something that would require a copy of your project to review, and you might want to consider filing a case with the Xilinx Technical Support since you are seeing an Internal Error.

Chris