DSP Tools

[syoma]

Hello

I have a problem by porting my design to Spartan-6. I'm exporting System Generator design to EDK as a Pcore. The EDK version is 13.2

During mapping I'm getting following errors:

ERROR:Place:1136 - This design contains a global buffer instance,
   <slave_core/slave_core/sysgen_dut/ce_16_sg_x21_BUFG>, driving the net,
   <slave_core/slave_core/sysgen_dut/ce_16_sg_x21_BUFG>, that is driving the
   following (first 30) non-clock load pins.

...

There are 3-4 similar errors with different nets:

ce_16_sg_x21_BUFG

ce_4_sg_x57_BUFG

ce_2_sg_x11_BUFG

etc.

I understood, that those nets are CE signals of different rates in my System Generator design. 

EDK recommends to put constraints in UCF file, such as:

PIN "slave_core/slave_core/sysgen_dut/ce_16_sg_x21_BUFG.O" CLOCK_DEDICATED_ROUTE = FALSE;

But I don't like it, because after each System Generator compilation I get another names of those nets and need to modify the UCF file manually.

Is there any other solution to fix these errors?

[chrisar]

Sysgen must be putting a BUFG on the clock enables in order to help with fanout.  This should be allowed, but if you are having problems you will probably need to add some constraints as was suggested.

Or you could modify the clock wrapper to remove these BUFGs.

This is the <design>_cw file in your project.

[syoma]

Sysgen must be putting a BUFG on the clock enables in order to help with fanout.  This should be allowed,

And how I can instruct Sysgen not to do that?

[syoma]

Hi all,

I still don't understand why the problem is coming. Sysgen knows how many BUFG my device has, and even from those only 6 of 16 are in use. What I'm doing wrong? Noone has such problem?