DSP Tools

[shanthibhushanb]

I have a problem which i have captured in the below document.The same error goes if am putting a delay block after the addition block.I dnt know much about the vhdl codes.can u help me with this problem

[bwiec]

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NgdBuild:604 - logical block 'four_anlog_out_x0/o2_1bb34a9b84/io_block_070b81180b/op5330_dac_if_with_wishbone_9712c341c2/op5330_dac_if_black_box' with type 'op5330_dac_if' could not be resolved. A pin name misspelling can cause this, a missing edif or ngc file, case mismatch between the block name and the edif or ngc file name, or the misspelling of a type name. Symbol 'op5330_dac_if' is not supported in target 'spartan3'.

NgdBuild:604 - logical block 'four_anlog_out_x0/op716x_io_block_e43a4224ff/io_block_234d42f288/op5340_adc_if_with_wishbone_3a2de1c78b/op5340_adc_if_black_box' with type 'op5340_adc_if' could not be resolved. A pin name misspelling can cause this, a missing edif or ngc file, case mismatch between the block name and the edif or ngc file name, or the misspelling of a type name. Symbol 'op5340_adc_if' is not supported in target 'spartan3'.

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Looks like you're using black boxed code from somewhere. My guess is that you're not seeing up your _config.m file properly to include all the necessary files.

[shanthibhushanb]

am not using any block box..so what can be the problem..

[vsrunga · Accepted solution]

Hi

You may not using black boxes knowingly, but primary reason for this error is that your project is missing EDIF files. During synthesis, the synthesis tool has probably created black_boxs for some of the modules, during implementation the tool needs all the EDIFs of the modules which were created black boxes. You need to go through your synthesis report and see what modules were created black boxes and why. you may probably have to look at your RTL to find out why black boxes were created.

Regards,