05-14-2012 09:11 AM
I have a problem which i have captured in the below document.The same error goes if am putting a delay block after the addition block.I dnt know much about the vhdl codes.can u help me with this problem
Solved! Go to Solution.
05-14-2012 10:09 AM
NgdBuild:604 - logical block 'four_anlog_out_x0/o2_1bb34a9b84/io_block_070b8118
NgdBuild:604 - logical block 'four_anlog_out_x0/op716x_io_block_e43a4224ff/io_b
Looks like you're using black boxed code from somewhere. My guess is that you're not seeing up your _config.m file properly to include all the necessary files.
05-19-2012 03:38 AM
You may not using black boxes knowingly, but primary reason for this error is that your project is missing EDIF files. During synthesis, the synthesis tool has probably created black_boxs for some of the modules, during implementation the tool needs all the EDIFs of the modules which were created black boxes. You need to go through your synthesis report and see what modules were created black boxes and why. you may probably have to look at your RTL to find out why black boxes were created.