DSP Tools

[giorgos2]

Hello,

I am trying to generate VHDL code for my system-generator system, but i am facing problem below:

Summary of Errors:

Error 0001: caught standard exception

Block: Unspecified

--------------------------------------------------------------------------------

Error 0001:

Reported by:

Unspecified

Details:

standard exception: XNetlistEngine:

An exception was raised:

com.xilinx.sysgen.netlist.NetlistInternal: time value is outside

permissable range

Unfortunately i can imagine what can cause this problem. Could anybody help me?

[sidharthg]

Go into the sysgen folder in your project.

Check out the above mentioned file  "com.xilinx.sysgen.netlist.NetlistInternal" and search for time value.

Hope this helps.

Sid 

[criley]

Check out Xilinx's Master Answer Record for standard exception errors and see if any of the solutions resolve the problem:

http://www.xilinx.com/support/answers/29430.htm

You may also want to poke around your model and simply the FPGA clock period and Simulink System Period to find out if the "time value is outside permissible range" message is correct.   You can also set the "Block icon display" in the SysGen token to "Normalized sample periods" which is helpful in understanding where sample period change in the model.