DSP Tools

[travisdoll]

Hi,

I am having trouble with the specifying the sampling rate of a counter block and receiving a different rate at the output during runtime. For example, say I set the Counter block sampling rate to 2.5e-8. When I manually (Format->Sample Time Display->All) go and have simulink calculate the sample time legend everything is perfect, but when I run the simulation I get 2.0972e-8. This really messes things up because the sample rate of the sysgen is set to 2.5e-8. Also, when I try to run the simulation I get an error stating the following:

The periodic sample time 1.0 is not allowed because the ratio of this sample time over base rate (3.199999999E-013) is greater than the maximum value of uint32.

I would pull the example into this forum, but I do not have access to transfer a screenshot or .mdl to this computer. Any help is greatly appreciated. If I am not being clear enough feel free to ask me questions. Thanks!

Using the following

Matlab 2010b

Sysgen 12.4

Windows 7

[ywu]

It will help if you can attach your model. Something you may want to try is to change the solver to "Fixed-Step" "Discrete". (Under Simulation->Configuration Parameters menu).

---

travisdoll wrote:

Hi,

I am having trouble with the specifying the sampling rate of a counter block and receiving a different rate at the output during runtime. For example, say I set the Counter block sampling rate to 2.5e-8. When I manually (Format->Sample Time Display->All) go and have simulink calculate the sample time legend everything is perfect, but when I run the simulation I get 2.0972e-8. This really messes things up because the sample rate of the sysgen is set to 2.5e-8. Also, when I try to run the simulation I get an error stating the following:

The periodic sample time 1.0 is not allowed because the ratio of this sample time over base rate (3.199999999E-013) is greater than the maximum value of uint32.

I would pull the example into this forum, but I do not have access to transfer a screenshot or .mdl to this computer. Any help is greatly appreciated. If I am not being clear enough feel free to ask me questions. Thanks!

Using the following

Matlab 2010b

Sysgen 12.4

Windows 7

---

[travisdoll]

Hi Jim,

Thanks for the response. The solver options are set to fixed-step as discrete (no continuous states) with fixed-step size to auto. I would attach the model if possible, but given my circumstances that is not allowed. Sorry. Here is a description of the problem area of my model:

Using all Xilinx blocks:

2 input Mux with inputs of a counter (1 bit) for select port and constants as inputs followed by a delay of 2 and a delay of 16

Counter FS is 2x

inputs FS are 1x

To simplify the situation, I reduced the sampling rates to the following:

Sel Counter FS = 1600Hz

Mux Inputs FS = 800Hz

When using the manual sample time legend population method I get the following sample rates for each block specified, which are the correct rates:

Sel Counter Output FS = 1600Hz

Mux Inputs FS = 800Hz

Mux Output FS 1600Hz

1st Delay Output FS = 1600Hz

2nd Delay Output FS = 1600Hz

During runtime the following samples rates occur for each block are specified below:

Sel Counter Output FS = 0.0016Hz

Mux Inputs FS = 800Hz

Mux Output FS 1600Hz

1st Delay Output FS = 1600Hz

2nd Delay Output FS = 0.0016Hz

Thanks for any advice...sorry I can't post the model, but greatly appreciate the comments.

[travisdoll · Accepted solution]

Ok so I figured out my own issue. It has nothing to do with the counters, muxes, constants, etc. I am generating my subsystems dynamically for my overall system using add_block, add_line, and the such. In doing so I am not deleting the system generator each time and for some reason this has caused an issue. To solve my issue I deleted all non-top level system generator blocks and copied/pasted the top level system generator into each subsystem requiring the token. This seems to have taken care of the error. The sampling rates seem a bit weird from time to time, but everything runs as expected. Also, I changed the Block Icon Display in the system generator options verify the samling rates and all is ok there. It seems that the Sample Time Display does not exactly match the correct sampling rates of xilinx blocks during runtime. Hopefully this helps someone else out in the future. Thanks for the advice Jim, your comment got me thinking about things further.