DSP Tools

[mafgani]

Hi,

I was trying to use the shared FIFO blocks in System Generator to perform data transfer during hardware co-simulation but have run into some unexpected behaviour.

Since the hardware clock is in "free-running" mode, I want to make sure that there are at least 'X' words left in the buffer before I start to read from it in order to comply with the requirements of my particular application. To achieve this, I tried to make use of the '%full' port of the FIFO block as shown in ExampleA.mdl. Unfortunately, the hardware co-simulation token generated from this design simply fails to work. After including the generated hw-cosimulation token in Example_tb.mdl, I set the clock source to "free-running" and select an appropriate network interface. However, when the design is run, the simulation time stays at zero and after some time, there is a pop-up with the error shown in the attached screenshot file. Essentially, the tool complains that it timed out while waiting for sufficient storage space to become available in the FIFO.

This does not make much sense since the control logic based on the '%full' port should make sure that the buffer is emptied if it is indeed full ...

I also include a second design (ExampleB.mdl) where everything is identical with the exception that the '%full' value is not used to control the FIFO.. This design runs without any problems ...

I am using ISE/SysGen 12.2 with MATLAB R2009b. The hardware co-simulation platform in use is a Xilinx ML402 board.

I hope a solution can be found quickly since I need this to work quite urgently ...

[baesae]

Hi mafgani

Eventhough this post is very old, I'd like to append my proposal.

I found your post when I was searching for a solution of my problem concerning the '%full' output of the "TO/FROM FIFO" block. Yours seems to rely on the same misbehaviour I experienced.

It seems to me that the '%full' output of the "From FIFO" as well as the "TO FIFO" block does NOT represent the percentual part the FIFO is filled. When the FIFO is 50% full, the output '%full' will be (in binary): 0.11111111.. (depending on the precision). Thus the '%fill' output is twice as big as it should be.

Consequently FIFO is 25% full when the output is 0.01111... and so on.

This is why your output logic did not work correctly.

XILINX-EMPLOYEES: Would you please verify the behaviour I described and confirm it to me? This could be a easily fixable bug :)

[baesae]

I need to correct myself.

It depends on the precision whether the %full output is correct.

Whereas with 1 bit precision it does not behave as expected (when 25% full, the 1 bit precision bit is set), with 3 or more bits it seems to run properly.

With 2 bits I do not understand what it is doing. For a FIFO with length 512 it outputs 0.10bin (0.5) when I stored about 192 samples..?!