DSP Tools

[tnikkane]

Hi!

I'm trying to simulate the output of a12-bit ADC with the Spartan-3AN starter kit. I have a Matlab function which produces a dataset, which represents the expected data from the real ADC. The dataset can include the ADC output values for e.g. 1 million clock cycles.  I was planning to use the System Generator in Matlab/Simulink to produce the functional block, which would loop this data and output it to the TX pins of the FPGA protoboard. However, it seems the System Generator can't include the dataset onto the FPGA design using the Simulink Sources/From File block. (Only Xilinx blocks are supported)

How would it be possible to use the dataset on the FPGA protoboard? I was thinking that the dataset could be maybe loaded on some type of memory on the protoboard. The memory would have to act quite fast though, because the system should output two channels of 12 bit wide parallel data with 10 MHz clock frequency. (The clock is external by the way)

I'm new to FPGA programming, so I hope that you could help me even though my questions might concern very basic stuff.

[ywu]

You would get faster response by posting System Generator related question on the DSP Tools board: http://forums.xilinx.com/t5/DSP-Tools/bd-p/DSPTOOL

You can load the file into variable first, then use the variable to initialize a ROM block in the Xilinx BlockSet.

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tnikkane wrote:

Hi!

I'm trying to simulate the output of a12-bit ADC with the Spartan-3AN starter kit. I have a Matlab function which produces a dataset, which represents the expected data from the real ADC. The dataset can include the ADC output values for e.g. 1 million clock cycles.  I was planning to use the System Generator in Matlab/Simulink to produce the functional block, which would loop this data and output it to the TX pins of the FPGA protoboard. However, it seems the System Generator can't include the dataset onto the FPGA design using the Simulink Sources/From File block. (Only Xilinx blocks are supported)

How would it be possible to use the dataset on the FPGA protoboard? I was thinking that the dataset could be maybe loaded on some type of memory on the protoboard. The memory would have to act quite fast though, because the system should output two channels of 12 bit wide parallel data with 10 MHz clock frequency. (The clock is external by the way)

I'm new to FPGA programming, so I hope that you could help me even though my questions might concern very basic stuff.

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[eilert]

Hi,

for test purposes you can use the ROM solution as proposed by Jim, but you might encounter some limitation in the BRAM capacity sooner or later.

12MBit is quite a number.

But there's a 16MBit SPI Flash on the board.

I think it can easily be written via JTAG.

Then you need some design to read out its contents and forward this data to your ADC-interface emulator.

Reference designs for reading the Flash should be available on the Xilinx website.

Creating or converting the data into promfiles for Impact shouldn't be too difficult.

Have a nice synthesis

  Eilert

[learner1]

Hi

You can digitize the signal in MATLAB and save it in a text file. Then you can red the file from the VHDL code you have written using predefined read and write functions. It can be a solution i think.

HIDIR