Hello,
looking for a tutorial to understund how to use the "EDK Processor" block in simulink so that a pcore for the design can be generated. in order to be integrated into EDK with a ublaze processor (FSL or PLB) . but I couldn't find any through google not even an explanation on how to do that.
Other question I have regarding the system generator, the timing requirement could not be met for a FIR Filter design onto a Xilinx University Program Virtex 2 Pro (on simulink) . I checked the same design by opening the ISE project generated. then the timing requirement is met. what would you think the problem is
Thank you
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Khlitoshi
