Hi
We are struggling to meet timing in a design for a
V5 SX95 which is about 50% full. We've had numerous timing problems
with the design, but solved most by using tight area constraints (We
have DACs running at 400Mhz which gave problems, but works with area
constraints).
Our current problem is more complicated
since the part of the design which gives the problems is a System
Generator design which forms part of the bigger design. Inside the
SysGen design, everything meets timing (using mostly pipelineing to
solve it) but the clock enables used inside the SysGen design are not
meeting timing. Since SysGen provides 3 clocking options, we've tried
all three of them but the only one that works with the blocks in our
design is the clock enable scheme. (Both Hybrid DCM and expose clock
ports does not work, mostly because blocks complain about not
supporting these schemes).
To solve this we've tried to
put the problematic CE's on global routes, but this in turn resulted in
unroutable paths in P&R. Another solution we tried was to put a
tight area constraint on the SysGen part of the design, but this
resulted in a fatal error in Map.
Thus, we are stuck. If you can think about more things to try, please let me know.
Thanks in advance,
Jaco
