DSP Tools

[amila_cabral]

Hello,

I'm trying to implement the example project "DSP48CoProcessor.mdl" in "...\Xilinx13_1\ISE_DS\ISE\sysgen\examples\EDK\DSP48CoProcessor" directory for spartan 6 board (Digilent Atlys). 

As mentioned in the "System Generator User Guide"

1. I have  created XPS project using BSB. Added UART and DDR2 memory controller. (Microblaze based)

2. Added an EDK block for "Processor subsystem" in "DSP48CoProcessor.mdl".

3. Imported the generated processor design by XPS.

4. Add memory map ports.

5. Configured System generator block for Hardware Co-sim using Ethernet.

6. Hit "Generate"

7.After running the XFLOW it gives the following error at the end

....................................................................................................................... 

ERROR:NgdBuild:467 - output pad net   'sysgen_hwcosim_iface_fpga_0_mcb_ddr2_mcbx_dram_addr_pin(12)' has an illegal   buffer

ERROR:NgdBuild:467 - output pad net   'sysgen_hwcosim_iface_fpga_0_mcb_ddr2_mcbx_dram_addr_pin(11)' has an illegal   buffer

ERROR:NgdBuild:467 - output pad net   'sysgen_hwcosim_iface_fpga_0_mcb_ddr2_mcbx_dram_addr_pin(10)' has an illegal   buffer   

ERROR:NgdBuild:467 - output pad net   'sysgen_hwcosim_iface_fpga_0_mcb_ddr2_mcbx_dram_addr_pin(9)' has an illegal   buffer

ERROR:NgdBuild:467 - output pad net   'sysgen_hwcosim_iface_fpga_0_mcb_ddr2_mcbx_dram_addr_pin(8)' has an illegal   buffer

ERROR:NgdBuild:467 - output pad net   'sysgen_hwcosim_iface_fpga_0_mcb_ddr2_mcbx_dram_addr_pin(7)' has an illegal   buffer

ERROR:NgdBuild:467 - output pad net   'sysgen_hwcosim_iface_fpga_0_mcb_ddr2_mcbx_dram_addr_pin(6)' has an illegal   buffer

ERROR:NgdBuild:467 - output pad net   'sysgen_hwcosim_iface_fpga_0_mcb_ddr2_mcbx_dram_addr_pin(5)' has an illegal   buffer

ERROR:NgdBuild:467 - output pad net   'sysgen_hwcosim_iface_fpga_0_mcb_ddr2_mcbx_dram_addr_pin(4)' has an illegal   buffer

ERROR:NgdBuild:467 - output pad net   'sysgen_hwcosim_iface_fpga_0_mcb_ddr2_mcbx_dram_addr_pin(3)' has an illegal   buffer

ERROR:NgdBuild:467 - output pad net   'sysgen_hwcosim_iface_fpga_0_mcb_ddr2_mcbx_dram_addr_pin(2)' has an illegal   buffer

ERROR:NgdBuild:467 - output pad net   'sysgen_hwcosim_iface_fpga_0_mcb_ddr2_mcbx_dram_addr_pin(1)' has an illegal   buffer

ERROR:NgdBuild:467 - output pad net   'sysgen_hwcosim_iface_fpga_0_mcb_ddr2_mcbx_dram_addr_pin(0)' has an illegal   buffer

ERROR:NgdBuild:467 - output pad net   'sysgen_hwcosim_iface_fpga_0_mcb_ddr2_mcbx_dram_ba_pin(2)' has an illegal   buffer

ERROR:NgdBuild:467 - output pad net   'sysgen_hwcosim_iface_fpga_0_mcb_ddr2_mcbx_dram_ba_pin(1)' has an illegal   buffer

ERROR:NgdBuild:467 - output pad net   'sysgen_hwcosim_iface_fpga_0_mcb_ddr2_mcbx_dram_ba_pin(0)' has an illegal   buffer

ERROR:NgdBuild:467 - output pad net   'sysgen_hwcosim_iface_fpga_0_mcb_ddr2_mcbx_dram_cas_n_pin' has an illegal   buffer

ERROR:NgdBuild:467 - output pad net   'sysgen_hwcosim_iface_fpga_0_mcb_ddr2_mcbx_dram_cke_pin' has an illegal   buffer

ERROR:NgdBuild:467 - output pad net   'sysgen_hwcosim_iface_fpga_0_mcb_ddr2_mcbx_dram_clk_n_pin' has an illegal   buffer

ERROR:NgdBuild:467 - output pad net   'sysgen_hwcosim_iface_fpga_0_mcb_ddr2_mcbx_dram_clk_pin' has an illegal   buffer

ERROR:NgdBuild:467 - output pad net   'sysgen_hwcosim_iface_fpga_0_mcb_ddr2_mcbx_dram_ldm_pin' has an illegal   buffer

ERROR:NgdBuild:467 - output pad net   'sysgen_hwcosim_iface_fpga_0_mcb_ddr2_mcbx_dram_odt_pin' has an illegal   buffer

ERROR:NgdBuild:467 - output pad net   'sysgen_hwcosim_iface_fpga_0_mcb_ddr2_mcbx_dram_ras_n_pin' has an illegal   buffer

ERROR:NgdBuild:467 - output pad net   'sysgen_hwcosim_iface_fpga_0_mcb_ddr2_mcbx_dram_udm_pin' has an illegal   buffer

ERROR:NgdBuild:467 - output pad net   'sysgen_hwcosim_iface_fpga_0_mcb_ddr2_mcbx_dram_we_n_pin' has an illegal   buffer

....................................................................................................................... 

I search the forum and found http://www.xilinx.com/support/answers/33125.htm .

I tried applying "edkprocessor_ddr2fix.m" for EDK block. (right click "Edit mask"->"Initialization" tab added as  "edkprocessor_ddr2fix(gcb);" ass done on Xilinx XAPP1136 ). I have change the port  names of "edkprocessor_ddr2fix.m" accordingly.

But I'm still having the above error.

Please help.............

Amila

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Please Note: system.ucf in XPS project has only 

Net fpga_0_MCB_DDR2_rzq_pin IOSTANDARD = LVCMOS18_JEDEC;

 Net fpga_0_MCB_DDR2_zio_pin IOSTANDARD = LVCMOS18_JEDEC;

these two pads dedicated for DDR2 memory

[xud]

Sysgen doesn't support adding MIG design as a black box, or added as a EDK submodule.

[amila_cabral]

Xillinx application note Xilinx XAPP1136  shows how VFBC implemented with DDR2 and hardware co-sim in sysgen.(I have added the DDR2 controller the same way it is mentioning) . Please correct me if I am wrong.

[amila_cabral]

Hello

 If you know anything related to testing  Xilinx XAPP1136  by creating own project,  please be kind enough to let me know immediately. I'm in amiddle of implementing a huge project that needed to be completed in couple of months time.

[xud]

Yes. I've heard of that application note. It uses MPMC not the MIG standalone. You can use it as a start point. It hasn't been tested in the later version. You can only use it as it was.

The difficulty here is how to handle bi-directional and clock I/Os when you generate non-memory map port. By default, tool will always IBUF for input and OBUF for output. Once you solve this issues, the error will be fixed.

[amila_cabral]

I'm using the  MPMC for DDR2.

I have not much experience in working with the System Generator. Is there anyway to specify SYSGEN,   "not to add buffers"  for the above ports during XFLOW.

Thank you.

[xud]

I'm not familar with MPMC. In ISE, normally you can add attribute BUFFER_TYPE in the source code, and then send the value to none. For more details about this attribute, please refer to page 356 of http://www.xilinx.com/support/documentation/sw_manuals/xilinx13_1/xst_v6s6.pdf

I haven't tested it yet, not sure whether it actually works or not. In the mean time you can take a look at the design file from that application note.