DSP Tools

[balta]

Hello, everyone. I made simple model in Simulink for hardware cosimulation in free running mode acording to xapp1031.pdf (http://www.xilinx.com/support/documentation/application_notes/xapp1031.pdf) and I choosed "Free-Running Simulation with Shared Memories Configured as
Shared FIFOs" type of hardware cossimulation.

So, Simulink model consists of (from left to right) : sine generator -> convert block - > buffer -> Shared memory write (Xilinx shared memory write block) to "CA"

in the middle is subsystem containing  From FIFO "CA" -> multyply by 2 -> TO FIFO "VA"

the last part of the model is  Shared memory read (Xilinx shred memory read block) -> unbuffer -> scope, and I had Spartan 3AN starter kit.

My problem is that every time I start simulation or generation of hardware cosimulation library, I get the error : 

"The Shared Memory Read block timed out while waiting for sufficient FIFO memory to become available"

I checked settings for sample time of  Shared memory read (Xilinx shared memory read block) and Shared memory write (Xilinx shared memory write block) and tried diferent from  xapp1031.pdf, but nothing happened.

I cannot figure out what is happening,  so, if anyone has idea where solution may be I will  be very grateful to hear it.

Thank you in advance

[mark.wheeler]

I downloaded the ZIP file that contained the examples used for this application note.  I was hoping to replicated their perfromance results using  the lastest tools.     However, I ran into this same snag.    Running a search on Google brought me to your post.    If you found a solution, please post it.

Begin generation
Checking model status
Checking simulation times
Performing compilation and generation

*** ERROR ***

Errors occurred during netlist generation.
Error reported by S-function 'xlfromshmem' in 'implementation_6_software/Shared Memory Read':

-- The Shared Memory Read block timed out while waiting for sufficient FIFO memory to become available.

[balta]

Hello, I abbandoned that solution and start writting direct in VHDL. It seems that problem was speed VS. synchronisation. If you want fast execution of both algorithms (FPGA hardware and Simulink) they need to be separate, without synchronisation or constant transfer between FPGA and Simulink via JTAG. If You want synchronisation, a big amount of time is spend on sending updates via JTAG between FPGA and Simulink. The thing get complicated if You want to have feedback, o man...  The soulution is maybe to make some buffer interface, but in free running mode, I dont know...

The another bug is in one of mdl libraries for generating the blocks for Hardware cosimulation option, it took me time to find error in xml in mdl file, smth about quotes if I remember. I could try to find it if you get the error for this

It was a couple months ago, so excuse me if I said something offtopic :), I turned to VHDL.

Pozdrav

[mark.wheeler]

Thanks for the info.   Using the files from the original ZIP, and just running the sotware simulation (test case #6), I will get this error.    I have not changed any of the default settings and assume everything worked when they first ran this benchmark.    The version of ISE and Mathworks were much older and I am guessing at least the problem I am seeing is caused from running the latest tools.

I had also assumed (word is very fitting) that I would not run into any snags when using Xilinx's own demos.  I don't have enough time to try and debug their problems.   This was more just an evaluation to see where they were with the tools and see if they could be used.    No support, many bugs, I think your making the right choice...

Thanks again.

[balta]

You are welcome, but dont give up VHDL, it is briliant!

[mark.wheeler]

Was looking to try and reduce development times with these tools.   As we continue to push more signal processing into the hardware, time to developed and maintain using HDL goes into overload.   Being able to leverage test benches and HLD from a tool like Matlab (which we already use) could very well save us a lot of time.   

Of course if I can't even get the manufactuer's basic examples working, I don't see it being a viable tool just yet.  

[nathanx]

We have an example "macfir_hw_w_frames_tb.mdl", which is located at C:\Xilinx\12.1\ISE_DS\ISE\sysgen\examples\shared_memory\hardware_cosim\frame_acc. This is ISE 12.1 installation directory. Take a look at the example and try to use shared memory in the same way as the example.

The shared memory timeout error message is misleading, it does not tell us the root cause of the issue. So you need to check all the settings in your model.

If you've any difficulty determing the cause, feel free to open a case at Xilinx Technical Support.

[mark.wheeler]

I am using the latest tools.  So, ISE 12.2.    The example you suggested (which is the same as the application note) when used with the latest Mathworks, will throw the Reference to non-existent field error once generated.   However, like with the example in the application, ignore the error and attempt to run it will upload the core to the 506 board and then output the following error:

Error reported by S-function 'xlfromshmem' in 'macfir_hw_w_frames_tb/Shared Memory Read':

-- The Shared Memory Read block timed out while waiting for sufficient FIFO memory to become available.

Same errors, which is no surprise as the diagram appears the same.   Again, I assume there is a bug in the Xilinx tools not supporting the latest Mathworks tools, or at least when using a 64-bit OS and the 64-bit tools.   

I will see if we can get Xilinx to put on a demo for us, using all the latest tools.  

[nathanx]

Which version of Matlab are you currently using? I have run the example I poined out to you with Matlab R2009b and the model works fine in hw co-sim. Check if you use free running clock, single-step clock will not work.

If the issue persists, I would suggest you contact Xilinx Technical Support.