DSP Tools

[vikasbhatia]

Hi

I have my own VHDL designs which i need to import as Black Boxes in SysGen. The issue is that VHDL designs that do not use any packages (defined exclusively by me) run fine; but in those design where i use my own packages (containing custom definitions,types, etc.) the outputs do not show anything in the simulator or simulink display. Also i need to know the correct order of  "this.add" statements  for config.m files for compilation

pls help me out !!!!

Thnks

[jeffreyh]

The order listed in the _config.m file should be  the correct compilation order, that is lower level modules should be compiled first before the top level file which should be listed last.

Unfortunately we don't have documentation on how to do this or have any examples.  I believe you should be able to use packages if you are using Modelsim for your HDL co-simulator.  I believe would need to specify a custom .do file with command.  For ISIM I'm not sure if this can be done.  Please open a support case for additional information or to request an enhancement to the flow.

[delbotero]

Hello,

I want to create a BLACK BOX for a VHDL module.

In my module the input is defined like a new type mat_nm defined by me in a package .

--------------------------------

entity test is
  port
  (
    clk : in std_logic;
    ce : in std_logic;

    input_a : in mat_nm;
    
    output_b : out std_logic_vector(31 downto 0)
    
  );
end correlator_n_inputs;

-----------------------------------------------------------

type row_n is array (COLS-1 downto 0) of std_logic_vector(7 downto 0);
type mat_nm is array (ROWS-1 downto 0) of row_n;

-----------------------------------------------------------

Question : How to add my package to Matlab? I have the next error

"PORT MUST BE DECLARED AS STD_LOGIC_VECTOR OR STD_LOGIC"

Regards,

DABG

[ywu]

For the top level ports on the blackbox, you will need to stay with std_logic and std_logic_vector for port types.

---

delbotero wrote:

Hello,

I want to create a BLACK BOX for a VHDL module.

In my module the input is defined like a new type mat_nm defined by me in a package .

--------------------------------

entity test is
  port
  (
    clk : in std_logic;
    ce : in std_logic;

    input_a : in mat_nm;
    
    output_b : out std_logic_vector(31 downto 0)
    
  );
end correlator_n_inputs;

-----------------------------------------------------------

type row_n is array (COLS-1 downto 0) of std_logic_vector(7 downto 0);
type mat_nm is array (ROWS-1 downto 0) of row_n;

-----------------------------------------------------------

Question : How to add my package to Matlab? I have the next error

"PORT MUST BE DECLARED AS STD_LOGIC_VECTOR OR STD_LOGIC"

Regards,

DABG

---

[delbotero]

Hello,

So does it mean that if my BLACK BOX has a matrix of 10x10 STD_LOGIC_VECTORs I have to connect all of them manually?

Thanks,

Regards,

DABG