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Contributor
evgenia89
Posts: 36
Registered: ‎02-06-2012
0
Accepted Solution

Using of Dual Port RAM

Hello!

 

Can anyone explain me how to use the block Dual Port RAM in Simulink? I am especially confused with meaning of ports addra and addrb.

 

Thanks!

 

Evgenia.

Super Contributor
vlavruhin
Posts: 195
Registered: ‎12-08-2010
0

Re: Using of Dual Port RAM

Hello, Evgenia.

 

Dual Port RAM is ordinary RAM block with two access input/output ports: port A and port B. So you can independently access to common memory space through these two ports. For example, you can have concurrent reading of one memory cell using port A and writing of other memory cell using port B.

 

AddrA is address line of port A. AddrB is address line of port B.

 

There is a detailed description of Dual Port RAM block in System Generator Reference Guide:

http://www.xilinx.com/support/documentation/sw_manuals/xilinx13_4/sysgen_ref.pdf

Best Regards,
Vitaly.
Contributor
evgenia89
Posts: 36
Registered: ‎02-06-2012
0

Re: Using of Dual Port RAM

Hello, Vitaly,

 

I applied sine waveform to addrb port, then I sum two signals from A and B and apply this to addra port.
I choose with the help of MCode, when wea and web are enable:
if x < 1000
    z = true;
  else
    z = false;

 

The result is not what I expected...

 

Super Contributor
vlavruhin
Posts: 195
Registered: ‎12-08-2010
0

Re: Using of Dual Port RAM

[ Edited ]

Evgenia, what are your expectations?

 

How are Counter, Counter1 and Dual Port RAM blocks configured ?

 

What are initial values of the counters? If initial values are equal, then you will get write-write collision (simultaneous write attempt at same memory cell, which will result in NaN output).

Best Regards,
Vitaly.
Contributor
evgenia89
Posts: 36
Registered: ‎02-06-2012
0

Re: Using of Dual Port RAM

I expected increasing of the signal amplitude every cycle.

 

Configurations are:
RAM: Port A - read before write, port B - read after write;
Counter: initial value - 0, up to 1000;
Counter1: initial value - 1000, up to 2000;
Counter2: initial value - 0, up to 2000.

Super Contributor
vlavruhin
Posts: 195
Registered: ‎12-08-2010
0

Re: Using of Dual Port RAM

Ok, Evgenia.

 

What are parameters of 'AddSub' block?

 

What is at output of your model? Could you attach MDL file?

 

Best Regards,
Vitaly.
Contributor
evgenia89
Posts: 36
Registered: ‎02-06-2012
0

Re: Using of Dual Port RAM

[ Edited ]

Vitaly,


thank you for your patient, all the parameters are in the attached file.

 

Evgenia.

Super Contributor
vlavruhin
Posts: 195
Registered: ‎12-08-2010

Re: Using of Dual Port RAM

Am I right that the bitwidths of counters are 8 bit? I.e., the counter is able to count from 0 to 255 and can't reach value 1000.

Best Regards,
Vitaly.
Contributor
evgenia89
Posts: 36
Registered: ‎02-06-2012
0

Re: Using of Dual Port RAM

Vitaly, thank you for your help very much. I checked the bitwidths and modified the model and now it works ok.

 

But now I need to modify the model because I want to divide the AddSub output signal to 2 and apply it to dina port of Dual Port RAM. The problem is that i need to divide from the second cycle, because during the first cycle port A output is empty.

 

I am using MCode block. The MatLab code is following:

 

function z = divst(x, i);
if (i < 512) 
    z = x;
else
    z = xl_force(x, xlSigned, 11);
end

When I start simulation I get a message: 'Illegal type of port dinb', because output of the block MCode has type Fix_17_11 while I was expecting Fix_16_11.

Also I am wondering what block I can use for variable i. For now I put counter, but I understand that it is not good solution.

 

Best regards,
Evgenia.

Super Contributor
vlavruhin
Posts: 195
Registered: ‎12-08-2010

Re: Using of Dual Port RAM

Hello, Evgenia.

 

If you would like to divide samples by 2, if some condition is true, and do not divide if this condition is false, then you should shift bits of these samples.

 

Lets assume, you have 16 bits (at input and output): b15, b14, ..., b1, b0.

1) If you wouldn't like to have division, then output samples should be as input: out15 = in15, out14 = in14, ..., out1 = in1, out0 = in0.

2) If you would like to divide by 2, then output samples should be shifted: out15 = in15, out14 = in15, ..., out1 = in2, out0 = in1. And in0 sample should be dropped in that case.

 

The function xl_force() does nothing with samples. It just sets properties of data type in such manner, that Simulink knows that these samples should be interpreted differently (different data type, different binary point, and hence different range of decimal values).

 

So in your model, you should actually shift bits of samples in one case, and do not shift otherwise. To do it, use function xfix({xlSigned, 16, 10}, x) and xfix({xlSigned, 16, 10}, x/2).

 


evgenia89 wrote:

Also I am wondering what block I can use for variable i. For now I put counter, but I understand that it is not good solution.


Why not? You need to implement a delay. So one option is to use a counter, and other is to have a series of registers (but it's huge solution for long delay). Just make sure that your counter will stop after the condition is met.

Best Regards,
Vitaly.